Dell Products Inc.

Bi-Chong Wang

Madhusudhan Rangarajan

Vijay Bharat Nijhawan

Wuxian Wu

Austin Patrick Bolen

Jinsaku Masuyama

Dirie N Herzi

Robert J Volentine

Saurabh Gupta

A system and method for recovering from a configuration error are disclosed. A Basic Input Output System (BIOS) configures a memory associated with a node of an information handling system and enables a progress monitoring process during configuration of the memory. The memory is disabled if the BIOS determines that a configuration error occurred and a memory reference code associated with the memory is modified in order to prevent a reset of the information handling system.

System and method for recovering from a configuration error

Before initializing a memory of an information handling system, a method includes loading an image of a video option ROM code for a graphics interface device to a cache associated with a processor of the information handling system, and executing the video option ROM code to initialize the graphics interface device. The method also includes executing a memory reference code to initialize the memory, and while executing the memory reference code, providing status information from the graphics interface device.

System and method for providing instant video in an information handling system

In accordance with certain embodiments of the present disclosure, an information handling system is provided. The information handling system may include a plurality of processors, each processor comprising multiple cores, a memory system coupled to the plurality of processors, and a controller coupled to the plurality of processors. The controller may be configured to: receive a local system management interrupt (SMI) signal regarding an error associated with at least one of the multiple cores, determine that the received local SMI signal triggers a global SMI based on a global SMI trigger rule, cause the plurality of processors to enter a global system management mode (SMM), and log the error in a shared resource shared by the plurality of processors during the global SMM.

System and method for logging system management interrupts

Systems and methods for reducing problems and disadvantages associated with physically asymmetrical memory structures are disclosed. A method for configuring memories in an information handling system having a plurality of memories, each memory local to one of a plurality of nodes, and wherein at least one memory of the plurality of memories has a different memory capacity than at least one other memory of the plurality of memories is provided. The method may include determining a smallest memory capacity of the plurality of memories. The method may also include allocating a node-interleaved memory using a portion of each memory equal to the smallest memory capacity. For each particular memory not fully allocated to the node-interleaved memory, each portion of each particular memory not allocated to the node-interleaved memory may be associated with a node local to the particular memory.

System and method for memory architecture configuration

A test mode initialization system includes beginning a power-on self-test (POST) wherein the POST may be performed to determine whether a system under test is in a quick test mode, and in response to being in the quick test mode, initialize only a portion of all memory in the system under test and initialize only a portion of a plurality of central processor unit (CPU) cores.

Manufacturing boot process with minimal component initialization

Monitoring of boot progress for a multiprocessor information handling system is performed with a test module running on a CPLD. RAM integrated in the CPLD stores boot progress information passed through an I/O buffer located between the processors and the firmware that boots the processors. Downloading of the boot progress from the RAM to an external device, such as through a serial port, provides a processor trace that is analysis and debugging of the firmware by recording processor operations through the boot progress.

System and method for analyzing CPU performance from a serial link front side bus

A system and method of accessing memory within an information handling system are disclosed. In one form, a method of accessing memory can include detecting a first operating value of a first memory access node accessible to a first processor, and initiating operation of the first memory access node to a first data rate value. The method can also include initiating operation of a second memory access node to a second data rate value. In one form, the second data rate value can be different from the first data rate value. The method can also include enabling a first application access to either the first memory access node or the second memory access node via an operating system enabled by the processor.

System and method of accessing memory within an information handling system

System and methods for preventing an operating-system scheduler in a computer system from crashing as a result of an uncleared periodic interrupt are disclosed. A periodic interrupt is generated using a real-time clock (RTC) residing on a chipset. A flag indicating a periodic interrupt is entered into a status register associated with the RTC in firmware residing on the CMOS chip, if the status register indicates no periodic interrupt has been pending. An interrupt handler associated with the RTC attempts to handle the periodic interrupt, if pending. If the periodic interrupt is pending after a preset interval of time elapses, a basic-input-output system (BIOS) residing on a memory unit coupled to the chipset generates a system-management interrupt (SMI). If the periodic interrupt is pending after the preset interval of time elapses, a firmware SMI handler residing on the memory unit clears the pending periodic interrupts from the status register. A scheduler timer associated with the operating system is updated.

System and method for preventing an operating-system scheduler crash

A system and method is disclosed for managing system management interrupts in a multiprocessor system. The system described herein includes multiple processors, each of which may be directly coupled to memory. A primary processor will recognize the initiation of a system management interrupt. The primary processor will write a reason code to a storage location and set a watchdog timer, the expiration of which causes all of the processors of the system to enter a system management mode. After all of the processors have entered system management mode, it is determined if the reason code of the storage location corresponds to certain software-based system management interrupts. If so, the system management interrupt is handled by the local processors. Following the handling of the system management interrupt by the local processor, a signal is sent to each of the other processors to cause the processors to exit system management mode.

System and method for managing system management interrupts in a multiprocessor computer system

An information handling system is disclosed and can include a processor and a memory coupled to the processor. Further, the system can include a system reserved area that is accessible to the processor. The system reserved area can include a physical memory fault table having a plurality of bits and each bit in the physical memory fault table can represent an equal block of the memory.

System and method of dynamically mapping out faulty memory areas

A system and method is disclosed for enumerating multi-level processor-memory affinities for non-uniform memory access systems. A processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in an information-handling system is calculated using at least two characteristics relating to memory-access speed that describe how the microprocessors and memory units are arranged in the information-handling system. The information-handling system then performs an algorithm on each processor-memory affinity hierarchy to obtain processor-memory affinity values in the information-handling system, and populates a table using the processor-memory affinity values. An operating system in the information-handling system can use the table to allocate memory units among microprocessors in the information-handling system.

Growing community of inventors

Austin, TX, United States of America

Bi-Chong Wang