Dell Products Inc.

International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Dell & Products L.p.

Emc IP Holding Company LLC

Dell Poducts L.p.

Bhyrav M Mutnury

Sandor Tibor Farkas

Moises Cases

Stuart Allen Berke

Nam Huu Pham

Umesh Chandra

Terence K Rodrigues

Arun Reddy Chada

Daniel N De Araujo

Bradley Donald Herrman

Pravin S Patel

Vadhiraj Sankaranarayanan

Chun-Lin Liao

Bhavesh Govindbhai Patel

Erdem Matoglu

Minchuan Wang

Douglas Winterberg

Mallikarjun Vasa

Kevin Warren Mundt

Vijendera Kumar

Wan-Ju Kuo

Caleb James Wesley

Timothy Michael Lambert

Raymond Dewine Heistand, Ii

Nanju Na

Sanjay Kumar

Daniel Mark Dreps

Justin Potok Bandholz

Jinwoo Choi

Tae Hong Kim

Vinh B Lu

Ching-Huei Chen

V Mallikarjun Goud

Douglas E Wallace

Mark Smith

Kent Barclay Howieson

Samuel R Connor

Bruce James Wilkie

William Andrew Smith

Bruce Roy Archambeault

Mark A Smith

Navraj Singh

Vijender Kumar

Han Deng

Jiayi He

Steven Richard Ethridge

William Gabriel Pagan

Christopher Collier West

Robert J Christopher

Peter Robert Seidel

Nickolaus J Gruendler

Wallace Huson Ables

Rubina Firdaus Ahmed

Yeshaswy Rajupalepu

Hamza S Rahman

Bradley D Herman

Thomas D Pahel

Vadhiraj Sankaranarayanana

Doug S Winterberg

Roshan Pai

Chandra V Krishnaswamy

Malikarjun Vasa

Paul A Boothe

Scott Lee Winters

Saravanan Sethuraman

James Anthony Pafumi

Isaac Qin Wang

Wade Andrew Butcher

Andrew Butcher

Mickey Steven Felton

James P Allen

Sanket Rathi

James Joseph Parsonese

Anil Bindu Lingambudi

Shiva R Dasari

Byron Lee Krauter

Kiran Kumar Anumalasetty

Sudhir Maddali

Robert G Bassman

Stephen M Tee

Candice Leontine Coletrane

Joseph Curtis Diepenbrock

Sandburg Hao Hu

Sanjiv Sinha

Jaydev M Reddy

Richard Daniel Trotta

Lynn Lingyu Kong

Prashant Sreedharan

Manish Sharma

Lingyu Kong

Girish Kumar Singh

Venkata Naga Seshaiah Anumula

Chi-Hsiang Hung

Nikita Ambasana

Pei-Yang Weng

Mioses Cases

Vasa Mallikarjun Goud

Bruce J Wilke

Oliver R Fasterling

An information handling system includes a PCB, a transmitter for a data communication interface, a receiver for the data communication interface, a first channel instantiated in the printed circuit board, and a second channel instantiated in the printed circuit board. The receiver includes a first input and a second input. The first channel is coupled between an output of the transmitter and the first input of the receiver and is routed in a first path in the printed circuit board. The second channel is coupled to provide a reference voltage to the second input of the receiver and is routed in a second path in the printed circuit board. At least a portion of the second path is routed adjacent to a portion of the first path.

Noise cancellation in low-speed signals

A printed circuit board includes a dielectric and a connector. The dielectric has a first dielectric constant. A first area within the dielectric has a second dielectric constant. The connector is mounted on the dielectric. The connector includes a first connector lead mounted on the dielectric, a first contact point above the dielectric, and a first connector wipe. The first connector wipe is disposed above the first area.

Signal speed increase in a connector wipe

In one or more embodiments, a printed circuit board (PCB) may be configured for reduced insertion loss between traces. Two traces on different layers may be connected by two vias and two connector traces on different layers, wherein one connector trace may have a first length and a second connector trace may have a second length that is longer than the first length such that a first portion of a signal transmitted along a first signal path through the first connector trace arrives at the second trace at substantially the same time as a second portion of the sign transmitted along a second signal path through the second connector trace.

System and method to maintain signal integrity between multiple signal paths connecting two traces in a printed circuit board

A printed circuit board includes a dielectric and a connector. The connector is mounted on the dielectric. The connector includes a first connector lead, a first contact point, and a first connector wipe. The first connector wipe includes a plurality of low impedance bumps. The low impedance bumps create an impedance mismatch between the first connector lead and the first connector wipe.

Reflective cancellations in a connector wipe of a surface mount connector

A printed circuit board comprising a first connection pad coupled to a first portion of a microstrip trace and a second connection pad coupled to a second portion of the microstrip trace. The microstrip trace has a first impedance along the first portion and a second impedance along the second portion. The printed circuit board also includes a conductive plane on a top surface of the microstrip trace, wherein the conductive plane includes a plurality of cutouts to reduce impedance mismatch between the first impedance and the second impedance.

Impedance tuning of microstrip traces

A receiver includes an ODT network and a signal eye sampler. The ODT network terminates a data communication interface at a selectable impedance including a nominal impedance, at least one higher impedance, and at least one lower impedance. The signal eye sampler determines an eye margin for data received on the data communication interface. The receiver selects the nominal impedance, determines a nominal eye margin associated with the nominal impedance, selects a delta impedance from one of the higher impedance and the lower impedance, determines a delta eye margin associated with the delta impedance, determines whether the delta eye margin is greater than the nominal eye margin, and sets a run time impedance value for the data communication interface to the delta impedance when the delta eye margin is greater than the nominal eye margin.

On-die termination optimization

A printed circuit board includes a dielectric material, a signal trace on a surface of the dielectric material, a signal layer within the dielectric material, a via including plating, and multiple back drill locations. The plating provides an electrical communication between the signal trace and the signal layer, and the via has a diameter. The back drill locations are along a length of the via beyond the signal layer. A first combined diameter of the back drill locations at a bottom of the back drill locations is equal to the dimeter of the via. A second combined diameter of the back drill locations at a top of the back drill locations is greater than the dimeter of the via.

Printed circuit board with reduced via striping

A printed circuit board includes a dielectric and a connector. The connector is mounted on the dielectric. The connector includes a first connector lead, a first contact point, and a first connector wipe. The first connector wipe includes a first wider section adjacent to the first contact point. The first wider section creates an impedance mismatch between the first connector lead and the first connector wipe.

Reflective cancellations in a connector wipe

A method may include transmitting one or more first test signals to electrical pathways of a connector-cable interface between a cable and a test circuit board in the absence of mechanical stress applied by a mechanical stressor to the connector-cable interface, performing measurements for one or more signal equalization parameters based on resultant signals from the electrical pathways resulting from the one or more first test signals in the absence of and in the presence of mechanical stress applied by the mechanical stressor to the connector-cable interface, and based on differences between the measurements, determining whether or not the connector-cable interface has satisfied signal integrity requirements.

Systems and methods for testing cabled interconnects under mechanical stress

A method may include transmitting first test signals to electrical pathways of a connector-cable interface between a cable and a test circuit board in the absence of and in the presence of mechanical stress applied by a mechanical stressor to the connector-cable interface, performing vector network analysis measurements for one or more electrical parameters based on resultant signals from the electrical pathways resulting from the test signals in the absence of and in the presence of mechanical stress applied by the mechanical stressor to the connector-cable interface, transmitting one or more second test signals to electrical pathways of the connector-cable interface in the presence of mechanical stress applied by the mechanical stressor to the connector-cable interface, and based on differences between the vector network analysis measurements, determining whether or not the connector-cable interface has satisfied signal integrity requirements.

An information handling system includes a memory device and a processor. The memory device includes first data representing a thermal profile of a motherboard, and second data representing a circuit trace of the motherboard. The circuit trace provides a high-speed data interconnection between two or more circuit devices. The processor determines an average temperature of the circuit trace on the motherboard based upon the first data and the second data, and models a trace layout for the circuit trace on the motherboard based upon the average temperature.

Integrated thermal-electrical co-simulation

A system to minimize effects of ground plane noise, including a processing unit including a first transmitter, a first receiver, and a first transistor, wherein the first transistor is coupled to the first receiver, the first transistor associated with a first ground voltage; and a memory device including a second transmitter, a second receiver, and a second transistor, wherein the second transistor is coupled to the second receiver, the second transistor associated with a second ground voltage; wherein the processing unit is coupled to the memory device, wherein the first transistor is coupled to the second transistor, wherein, when the processing unit is transmitting data to the memory device, the processing unit enables the first transistor and the memory device disables the second transistor such that a second threshold voltage associated with the second receiver is adjusted based on the first ground voltage.

System to minimize effects of ground plane noise

A computing cable that connects computing elements, including: a trace including a first trace segment and a second trace segment, the trace having a first impedance; and an attenuator connecting the first trace segment to the second trace segment, the attenuator including: a resistor having a resistance, and a conductor having a second impedance, wherein the combination of the resistance and the second impedance is based on the first impedance.

Loss-controlled computing cable

A system for preventing crosstalk between adjacent channels comprises a crossover connector positioned along a length of one channel such that a portion of a positive trace for a first channel is positioned adjacent to a positive trace of a positive trace of an adjacent channel. The position of the crossover connector is based on preventing crosstalk and crossover connectors on adjacent channels may be staggered to further prevent crosstalk. A crossover connector may be based on capacitors or resistors to prevent crosstalk.

System for crosstalk rejecting topology

Back drilling vias of a PCB, including: identifying a particular diameter of a particular via of multiple vias of the PCB; back drilling of the particular via with a first drill bit having a first diameter, the first diameter a first percentage greater than the particular diameter of the particular via; determining whether the first diameter of the first drill bit is a threshold percentage greater than the particular diameter of the particular via; determining that the first diameter of the first drill bit is less than the threshold percentage greater than the particular diameter of the particular via, and in response: back drilling of the particular via with a second drill bit having a second diameter, the second diameter a second percentage greater than the particular diameter of the particular via, the second diameter greater than the first diameter.

Back drilling vias of a printed circuit board

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Austin, TX, United States of America

Bhyrav M Mutnury