Dell Products Inc.

International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Emc IP Holding Company LLC

Dell Poducts L.p.

Bhyrav M Mutnury

Sandor Tibor Farkas

Moises Cases

Stuart Allen Berke

Nam Huu Pham

Umesh Chandra

Terence K Rodrigues

Arun Reddy Chada

Daniel N De Araujo

Bradley Donald Herrman

Pravin S Patel

Vadhiraj Sankaranarayanan

Chun-Lin Liao

Bhavesh Govindbhai Patel

Erdem Matoglu

Minchuan Wang

Douglas Winterberg

Mallikarjun Vasa

Kevin Warren Mundt

Vijendera Kumar

Wan-Ju Kuo

Caleb James Wesley

Timothy Michael Lambert

Raymond Dewine Heistand, Ii

Nanju Na

Sanjay Kumar

Daniel Mark Dreps

Justin Potok Bandholz

Jinwoo Choi

Tae Hong Kim

Vinh B Lu

Ching-Huei Chen

Douglas E Wallace

Mark Smith

Kent Barclay Howieson

Samuel R Connor

Bruce James Wilkie

Bruce Roy Archambeault

Mark A Smith

Navraj Singh

V Mallikarjun Goud

Han Deng

Vijender Kumar

Jiayi He

Steven Richard Ethridge

William Gabriel Pagan

Christopher Collier West

Robert J Christopher

Peter Robert Seidel

Nickolaus J Gruendler

Wallace Huson Ables

Rubina Firdaus Ahmed

Yeshaswy Rajupalepu

Hamza S Rahman

Bradley D Herman

Thomas D Pahel

Vadhiraj Sankaranarayanana

Doug S Winterberg

Malikarjun Vasa

Paul A Boothe

Scott Lee Winters

Saravanan Sethuraman

James Anthony Pafumi

Isaac Qin Wang

Wade Andrew Butcher

Andrew Butcher

Mickey Steven Felton

Sanket Rathi

James P Allen

James Joseph Parsonese

Anil Bindu Lingambudi

Shiva R Dasari

Byron Lee Krauter

Kiran Kumar Anumalasetty

Sudhir Maddali

Robert G Bassman

Stephen M Tee

Candice Leontine Coletrane

Joseph Curtis Diepenbrock

William Andrew Smith

Sandburg Hao Hu

Sanjiv Sinha

Jaydev M Reddy

Richard Daniel Trotta

Lynn Lingyu Kong

Prashant Sreedharan

Manish Sharma

Lingyu Kong

Girish Kumar Singh

Venkata Naga Seshaiah Anumula

Chi-Hsiang Hung

Nikita Ambasana

Pei-Yang Weng

Mioses Cases

Vasa Mallikarjun Goud

Bruce J Wilke

Oliver R Fasterling

Raymond D Heistand Ii

ChunLin Liao

James Chen

An information handling system includes a memory device and a processor. The memory device includes first data representing a thermal profile of a motherboard, and second data representing a circuit trace of the motherboard. The circuit trace provides a high-speed data interconnection between two or more circuit devices. The processor determines an average temperature of the circuit trace on the motherboard based upon the first data and the second data, and models a trace layout for the circuit trace on the motherboard based upon the average temperature.

Integrated thermal-electrical co-simulation

A system to minimize effects of ground plane noise, including a processing unit including a first transmitter, a first receiver, and a first transistor, wherein the first transistor is coupled to the first receiver, the first transistor associated with a first ground voltage; and a memory device including a second transmitter, a second receiver, and a second transistor, wherein the second transistor is coupled to the second receiver, the second transistor associated with a second ground voltage; wherein the processing unit is coupled to the memory device, wherein the first transistor is coupled to the second transistor, wherein, when the processing unit is transmitting data to the memory device, the processing unit enables the first transistor and the memory device disables the second transistor such that a second threshold voltage associated with the second receiver is adjusted based on the first ground voltage.

System to minimize effects of ground plane noise

A computing cable that connects computing elements, including: a trace including a first trace segment and a second trace segment, the trace having a first impedance; and an attenuator connecting the first trace segment to the second trace segment, the attenuator including: a resistor having a resistance, and a conductor having a second impedance, wherein the combination of the resistance and the second impedance is based on the first impedance.

Loss-controlled computing cable

A system for preventing crosstalk between adjacent channels comprises a crossover connector positioned along a length of one channel such that a portion of a positive trace for a first channel is positioned adjacent to a positive trace of a positive trace of an adjacent channel. The position of the crossover connector is based on preventing crosstalk and crossover connectors on adjacent channels may be staggered to further prevent crosstalk. A crossover connector may be based on capacitors or resistors to prevent crosstalk.

System for crosstalk rejecting topology

Back drilling vias of a PCB, including: identifying a particular diameter of a particular via of multiple vias of the PCB; back drilling of the particular via with a first drill bit having a first diameter, the first diameter a first percentage greater than the particular diameter of the particular via; determining whether the first diameter of the first drill bit is a threshold percentage greater than the particular diameter of the particular via; determining that the first diameter of the first drill bit is less than the threshold percentage greater than the particular diameter of the particular via, and in response: back drilling of the particular via with a second drill bit having a second diameter, the second diameter a second percentage greater than the particular diameter of the particular via, the second diameter greater than the first diameter.

Back drilling vias of a printed circuit board

A test system is provided for determining that data channels on a printed circuit board (PCB) have a predetermined impedance level. Each channel in the PCB is terminated at the predetermined impedance level. The PCB has a receptacle for coupling a device to the channels. An instrument can be installed into the receptacle, and includes connections to each of the channels, and a connector that is coupled to the connections by a channel splitter network. A test device is coupled to the connector and provides a test signal to the connector, receives a return signal from the connector, and determines that at least one of the channels does not have the predetermined impedance based upon the return signal.

Channel impedance measurement instrument

An integrated circuit device includes a multiplexor and multiple receivers for high-speed data communication interfaces. The multiplexor includes multiple signal inputs, a selector input, and a signal output. Each receiver includes a differential data signal input including a positive signal input and a negative signal input, a first termination resistor to terminate the positive signal input to a reference voltage node, a second termination resistor to terminate the negative signal input to the reference voltage node, and a noise measurement node to detect common mode noise at the reference voltage node, the noise measurement node coupled to an associated one of the signal inputs.

Common mode noise measurement in multiple data communication interface receivers

A circuit includes an inductive circuit trace and a nonlinear device. The circuit conducts a signal input to a load. The circuit trace receives the signal input at a first end of the circuit trace and provides the signal input to the load at a second end of the circuit trace. The nonlinear device is coupled at the second end and is configured to increase a voltage rise time of the signal input.

Slew rate in low-speed data communication interfaces

A receiver for a high-speed data communication interface includes a differential data signal input, a first termination resistor, a second termination resistor, and a noise measurement node. The differential data signal input includes a positive signal input and a negative signal input. The first termination resistor terminates the positive signal input to a reference voltage node. The second termination resistor terminates the negative signal input to the reference voltage node. The noise measurement node is coupled to detect common mode noise at the reference voltage node.

Common mode noise measurement in a data communication interface receiver

A printed circuit board includes metal layers, a metalized circuit via interconnecting a first one of the metal layers and a second one of the metal layers, and a back-drill hole drilled to remove metalization of the circuit via from a third metal layer adjacent to the second metal layer to a fourth metal layer at a first surface of the printed circuit board. The back-drill hole has a profile that includes a first undercut at a bottom of the first back-drill hole.

System and method to eliminate via striping

A processing device includes a transmitter, a difference amplifier, and a data detector. A first output buffer of the transmitter receives data and has a first output coupled to a channel that is designed to have a first impedance value, but that has a second impedance value that which may or may not be equal to the first impedance value. A second output buffer of the transmitter receives the data and has an output coupled to a circuit that has the first impedance. The difference amplifier has inputs coupled to the outputs of the first and second output buffers. The data detector is coupled to an output of the difference amplifier. The data processing device operates in a test operation mode to provide test data to the first and second output buffers and to determine whether the second impedance is equal to the first impedance based on information from the data detector.

On-die channel impedance verification

An inhomogeneous dielectric medium high-speed signal trace system includes a first and second ground layer. A first dielectric layer is located adjacent the first ground layer. A second dielectric layer has a different dielectric constant and a greater thickness than the first dielectric layer, and is located between the first dielectric layer and the second ground layer. A first differential trace pair is located between the first dielectric layer and the second dielectric layer, and includes a trace spacing that is less than or equal to a thickness of the first dielectric layer. The first different trace pair transmit signals and, in response, produces a magnetic field, and the trace spacing prevents a magnetic field strength of the magnetic field from exceeding a magnetic field strength threshold at a second differential trace pair that is located adjacent the first differential trace pair.

Inhomogeneous dielectric medium high-speed stripline trace system

A connection assembly including a receptacle connector having a first and a second end, including: a shell, including a first outer surface and a second outer surface; a shield surrounding the shell, the shield including: a first portion including a first cam flange, the first portion rotatable about a first spring hinge; a second portion including a second cam flange, the second portion rotatable about a second spring hinge; a mating connector removable coupleable to the receptacle connector, including: an adjustment member, wherein, when a positioning of the adjustment member is adjusted to decrease a distance between the adjustment member and the second end of the receptacle connector, the adjustment member adjusts a distance between the first cam flange and the second cam flange to rotate the first portion of the shield about the first spring hinge and rotate the second portion of the shield about the second spring hinge.

Connection assembly for use in an information handling system

A printed circuit board (PCB) includes first and second signal pads and a guard trace formed on a surface of the PCB. The first and second signal pads are for connecting to signal contacts of a high-speed data communication interface. The guard trace is located between the first signal pad and the second signal pad. The PCB further includes first, second, and third ground vias that couple the guard trace to a ground plane of the PCB. The first ground via is located at a first end of the guard trace. The second ground via is located at a second end of the guard trace. The third ground via is located between the first via and the second via.

Guard trace ground via optimization for high-speed signaling

A CPU includes a processor die and a substrate. The processor die includes first signal contacts, power contacts, and ground contacts. The processor die is affixed and electrically coupled to the substrate on a first surface of the substrate. The substrate routes the first signal contacts to associated second signal contacts on a second surface of the substrate. The substrate further routes a subset of the power contacts to a power pad on the first surface of the substrate, and routes a subset of the ground contacts to a ground pad on the first surface of the substrate.

CPU for heatsink based power delivery

Growing community of inventors

Austin, TX, United States of America

Bhyrav M Mutnury