Intel Corporation

Bhushan M Borole

Abhishek R Appu

Altug Koker

Wenyin Fu

Kamal Sinha

Joydeep Ray

Prasoonkumar Surti

Balaji Vembu

Nikos Kaburlasos

Anupama Ambardar Thaploo

Iqbal Rajwani

Travis T Schluessler

Kiran Chand Veernapu

Ankur N Shah

Sanjeev S Jahagirdar

Eric J Hoekstra

Vasanth Ranganathan

Kai Xiao

Linda L Hurd

Abhishek Venkatesh

Sunil Nekkanti

Elmoustapha Ould-Ahmed-Vall

Deepak Shashidhar Vembar

Jonathan Kennedy

Subramaniam M Maiyuran

Guei-Yuan Lueh

Michael Apodaca

Adam T Lake

David M Puffer

Atsuo Kuwahara

Aravindh V Anantaraman

Jeffery S Boles

Chandrasekaran Sakthivel

James A Valerio

Jacek Kwiatkowski

Pattabhiraman K

Josh B Mastronarde

Philip R Laws

Brent E Insko

Tomasz Janczak

Saurabh Sharma

David M Cimini

Radhakrishnan Venkataraman

Slawomir Grajewski

Eric J Asperheim

Anupreet S Kalra

Hugues Labbe

Bee Ngo

Muhammad M Khellah

Jaydeep P Kulkarni

Chandra S Gurram

Yoav Harel

Pascal Meinerzhagen

Eric Finley

Carlos Nava Rodriguez

Kenneth Brand

Hughes Labbe

Jeffrey S Boles

Phillip R Laws

In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.

System, apparatus and method for increasing performance in a processor during a voltage ramp

Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

Processor power management

Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.

Dynamic power budget allocation in multi-processor system

In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

Hybrid low power homogenous grapics processing units

An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.

Collaborative multi-user virtual reality

A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.

Frequent data value compression for graphics processing units

A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.

Replacement policies for a hybrid hierarchical cache

In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.

System, apparatus and method for segmenting a memory array

By predicting future memory subsystem request behavior based on live memory subsystem usage history collection, a preferred setting for handling predicted upcoming request behavior may be generated and used to dynamically reconfigure the memory subsystem. This mechanism can be done continuously and in real time during to ensure active tracking of system behavior.

Dynamically reconfigurable memory subsystem for graphics processors

Growing community of inventors

Rancho Cordova, CA, United States of America

Bhushan M Borole