Texas Instruments Corporation

Intersil Americas Inc.

Shaoxing Yuanfang Semiconductor Co., Ltd.

Bhupendra Sharma

Win Naing Maung

Huanzhang Huang

Douglas Edward Wente

Mustafa Ulvi Erdogan

Suzanne Mary Vining

Saurabh Goyal

Sandeep Kesrimal Oswal

Visvesvaraya Appala Pentakota

Ankit Seedher

Srinath Sridharan

Raja Prabhu J

Sudheer Prasad

Debasish Behera

Sandeep Sasi

Jeevabharathi G

Purva Choudhary

Giri N Rangan

Akash Gupta

Chandrashekar Bg

Nandini Ganig Bs

An electronic block includes multiple independent Phase-Locked Loops (PLLs) and a switch matrix. Each PLL has an input path and an output path. The switch matrix is operable to concurrently connect a respective signal on the output path of each PLL to the input path of another PLL. In an embodiment, each of the respective signals on the output paths is a corresponding frequency-correction signal generated by a low-pass filter (LPF) in the corresponding PLL. In an embodiment, each PLL includes a frequency-correction signal combiner to combine the frequency-correction signals received from any of the other PLLs with its own frequency-correction signal to form a combined frequency-correction signal. The combined frequency-correction signal is provided to a controlled oscillator in the PLL to generate an output clock of the PLL based on the combined frequency-correction signal. The frequency-correction signals may be analog or digital signals.

Inter-PLL communication in a multi-PLL environment

Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.

Embedded universal serial bus 2 repeater

At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving, at a circuit, data via a differential input signal, detecting a rising edge in the data received via the differential input signal, and precharging a common mode voltage (Vcm) node of the differential input signal responsive to detecting the rising edge in the data received via the differential input signal, wherein the Vcm node is a floating node.

Aspects of the disclosure provide for a circuit including a squelch detector having a first input coupled to a first node and configured to receive a positive component of a differential signal with a floating center tap, a second input coupled to a second node and configured to receive a negative component of the differential signal, and an output coupled to a logic circuit, a first resistor coupled between the first node and a third node, a second resistor coupled between the third node and the second node, a third resistor coupled between the first node and a fourth node, a fourth resistor coupled between the fourth node and the second node, a capacitor coupled between the fourth node and a ground terminal, a comparator having a first input coupled to the third node, a second input coupled to a fifth node, and an output coupled to the logic circuit.

Delta sigma modulators, apparatus and methods mitigate DAC error induced offset and even order harmonic distortion in a delta sigma modulator by chopping a digital output stream of a forward circuit path using a digital modulator or digital chopper circuit in a feedback circuit to create a DAC digital input signal responsive to a chopper clock signal having a clock rate lower than a DSM quantizer clock signal, and chopping a differential DAC output signal using an analog chopper circuit responsive to the chopper clock signal to provide a differential feedback signal to a forward circuit path of the DSM to mitigate DAC error induced offset and even order harmonic distortion in the digital output stream.

Delta sigma modulator apparatus and method to mitigate DAC error induced offset and even order harmonic distortion

Circuits, methods, and apparatus that provide bootstrapped switches having improved reliability. One example improves the reliability of a discharge transistor connected to discharge the gate of a switch transistor by decreasing its operating voltage during the discharge. This example provides a discharge transistor having a first source-drain region connected to a gate of a switch transistor. Since the gate of the switch transistor can reach high voltages, if the discharge transistor's second source-drain region is instantaneously tied to ground when the switch's gate is discharged, the discharge transistor's reliability can be degraded due to hot-electron effects. Accordingly, instead of being connected to ground&#x2014;or an intermediate node that quickly reaches the ground potential during gate discharge&#x2014;the second source-drain region of the discharge transistor is coupled to an intermediate node that discharges to ground at a slower rate.

Highly linear bootstrapped switch with improved reliability

Circuits, methods, and apparatus that provide sampling networks that avoid undesired transient voltages. One example provides a sampling network that includes a switch such that charge is transferred to an integrator in two separate steps instead of one. This switch connects the first side of a capacitor to an intermediate voltage after it is connected to an input voltage and before it is connected to a reference voltage, where the reference voltage is the output of a one-bit digital-to-analog converter. This intermediate switching allows charge to be transferred from a sampling capacitor to an integrating capacitor in two steps, thus avoiding undesirable transient voltages.

Input sampling network that avoids undesired transient voltages

Ensuring sufficient bias current is provided to a portion of a circuit containing low voltage transistors operating with a high supply voltage. Such a sufficient bias current may be ensured by generating a primary bias current from a low supply voltage and a backup bias current from a high supply voltage, and providing the backup bias current as the bias current if the primary bias current is not present. The primary bias current may be provided as the bias current when the low supply voltage is available. Thus, the backup bias current is provided as bias current in case of undesirable supply sequencing.

Avoiding excessive cross-terminal voltages of low voltage transistors due to undesirable supply-sequencing in environments with higher supply voltages

A technique to attenuate even-order harmonics of an output stage of a multistage nested Miller compensation circuit. In one example embodiment, this is accomplished by using a low-bandwidth low-swing amplifier in the common mode feedback loop to improve the even-order harmonic performance in the signal path. The technique uses a separate multistage loop for the common mode feedback loop to attenuate the even-order harmonics. The common mode feedback loop is the fourth stage and uses the third stage of the nested Miller compensation circuit. The fourth stage of the common mode feedback loop includes a single harmonic and uses a low voltage supply to achieve lower power consumption by the common mode feedback loop.

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Bengaluru, India

Bhupendra Sharma