Intel Corporation

C-cube Microsystems, Inc.

Tripath Technology, Inc.

Cirrus Logic Inc.

Bhupendra K Ahuja

Adya S Tripathi

Cary L Delano

Petro Estakhri

Paul M Romano

John S Geldman

Larry D King

Son H Ho

Phuc Tran

Maryam Imam

Palaksha Setty

Donald Sollars

A signal processing circuit is described including a frequency selective network in a feedback loop. An analog-to-analog converter in the feedback loop is coupled to the frequency selective network. A continuous-time feedback path provides feedback from the output terminal of the analog-to-analog converter to the frequency selective network.

Power efficient line driver

An improved current steering cell for a DAC which eliminates the need for an inverter reduces the noise at the common mode. The cell includes a first and a second current steering MOS transistor of a first polarity type, each having a gate and a pair of current passing terminals. The cell has an input terminal for receiving digital input signals coupled to the gate of the first of the pair of current steering transistors, and a common mode node for receiving an input current coupled to the same one of the pair of current passing terminals of each current steering MOS transistor. The current output terminal of the cell is coupled to the other of the pair of current passing terminals of the first of the current steering MOS transistors. Finally, the cell includes a third MOS transistor of the opposite polarity type to the current steering MOS transistors, having a gate and a pair of current passing terminals for passing a current through the transistor, the gate of the third MOS transistor being coupled to the gate of the first MOS current steering transistor, and the current passing terminals of the third MOS transistor being coupled between the gate of the second MOS current steering transistor and one of the pair of current passing terminals of the second MOS current steering transistor.

Current steering circuit for a digital-to-analog converter

A selectable reference voltage circuit for a digital-to-analog converter (DAC) which includes an input terminal for receiving an external reference voltage, a voltage comparator having two inputs and an output, one input for receiving the reference voltage and the other for receiving a predetermined voltage, the comparator providing one of two possible output voltages based upon the relationship of the magnitudes of the reference voltage and the predetermined voltage. The circuit includes a multiplexer having a control input coupled to receive as an input signal the output of the comparator, and having two inputs for receiving input voltage signals, one for receiving the voltage on the reference voltage input terminal and the other for receiving an on-chip generated reference voltage, the multiplexer selecting as an output voltage one of the two input voltages determined by the input signal at its control input. When there is a reference voltage at the reference voltage input terminal of the DAC, that voltage is supplied at the output of the multiplexer and used as the reference voltage for the DAC. When there is no reference voltage at the reference voltage input terminal of the DAC, the internally generated reference voltage is supplied at the output of the multiplexer and is used as the reference voltage of the DAC.

Selectable reference voltage circuit for a digital-to-analog converter

An integrated circuit controls the low level, electromechanical functionality of a computer mass storage device, such as a magnetic disk drive incorporating a spindle motor for rotatably controlling a disk and an actuator for positioning at least one read/write head with respect to the disk, to read or write encoded data configured in information data sectors and to sense encoded data of servo data sectors. A servo subsystem is coupled to an output of the read/write head for detecting the servo data sectors and providing a control signal in response thereto. An analog-to-digital subsystem is also coupled to an output of the read/write head and is operative in response to the servo subsystem control signal for converting the encoded data of the servo data sectors to digital transducer position information representative of a position of the read/write head with respect to the data tracks. A data processing subsystem is coupled to the analog-to-digital subsystem for processing the digital transducer position information and providing digital motion control signals in response thereto. A digital-to-analog subsystem is coupled to the data processing subsystem for providing analog control signals to the spindle motor and the actuator in response to the digital motion control signals.

Integrated circuit servo system control for computer mass storage device

A clock signal distribution network in a microprocessor of a computer system for distributing a global clock signal to a plurality of units of the microprocessor includes a clock generator for generating a first clock signal with an input delay. A phase locked loop circuit generates a controllable delay to the first clock signal to become the global clock signal. A clock driver drives the global clock signal to the plurality of units. An electrical connector includes a plurality of connection lines for coupling the global clock signal to the plurality of units. A length equalizer equalizes the signal transfer delay of each of the plurality of connection lines such that the global clock signal reaches each of the plurality of units via each of the plurality of connection lines at the same time. Each of the plurality of units includes an area buffer for standardizing its input load to the clock driver. A dummy buffer introduces the input delay of the clock generator to the global clock signal. The phase locked loop circuit controls the generation of the controllable delay to the first clock signal in response to the output signal from the dummy buffer such that the global signal received at each of the plurality of units is synchronized to the clock input signal independent of a process variation, a temperature variation, and a voltage supply variation.

Skew-free clock signal distribution network in a microprocessor of a

A clock signal distribution network in a microprocessor for distributing a global clock signal to a plurality of units of the microprocessor includes a clock generator for generating a first clock signal with an input delay. A phase locked loop circuit generates a controllable delay to the first clock signal to become the global clock signal. A clock driver drives the global clock signal to the plurality of units. An electrical connector includes a plurality of connection lines for coupling the global clock signal to the plurality of units. A length equalizer equalizes the signal transfer delay of each of the plurality of connection lines such that the global clock signal reaches each of the plurality of units via each of the plurality of connection lines at the same time. Each of the plurality of units includes an area buffer for standardizing its input load to the clock driver. A dummy buffer introduces the input delay of the clock generator to the global clock signal. The phase locked loop circuit controls the generation of the controllable delay to the first clock signal in response to the output signal from the dummy buffer such that the global signal received at each of the plurality of units is synchronized to the clock input signal independent of a process variation, a temperature variation, and a voltage supply variation. The method of eliminating clock signal in the clock signal distribution network is also described.

Skew-free clock signal distribution network in a microprocessor

A design for a high performance CMOS output buffers utilizing a process, supply and temperature conpensated current source to achieve very tight distribution of rise/fall times and propagation delays. The output buffer has been optimized to limit switching noise by using current controlled predrivers. An output buffer according to the present invention can switch up to a 100 pf load to TTL levels with rise times of no more than 4.0 ns and propagation delays ranging from 2.1 ns to 11.6 ns over the entire range of process, supply, temperature, and load for a typical one micron CMOS process; Vcc from 4.5 to 5,5V, temperature from -10 to 120.degree. C., and loads from 10 to 100 pf.

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Fremont, CA, United States of America

Bhupendra K Ahuja