Electronics and Telecommunications Research Institute

Korea Telecommunication Authority

Other

Bhum-Cheol Lee

Jung-Hee Lee

Seung-Woo Lee

Dae-Geun Park

Kang-Il Choi

Young-Ho Park

Kwon-Chul Park

Sang-Min Lee

Jong-Moo Sohn

Hyun-Yong Lee

Jin-Young Kim

Hyun-Yong Hwang

Eun-Chang Choi

Hee-Young Jung

Byung-Yun Lee

Young-sun Kim

Kyung-pyo Jun

Jeong-Hee Lee

Hyoung-Il Lee

Man-Soo Han

In-Tack Han

Kang-II Choi

Ick-Sung Choi

An apparatus for virtual switching includes a queue memory configured to store at least one queue; a data memory configured to store data; a mapper configured to classify the data into flows and store a point of the data in a queue mapped with the flows; a plurality of virtual machines configured to perform a process based on the data; and a virtual switch configured to extract the data from the data memory by referring to the point stored in the queue and transfer the data to the virtual machine, wherein the virtual switch transfers the data corresponding to a single queue to a single virtual machine.

Apparatus and method for virtual switching

An apparatus for parallel processing according to an example may include a queue memory configured to store one or more queues, a data memory configured to store data, a mapper configured to classify the data into flows and store a pointer of the data in a queue mapped with the flow; a plurality of processors configured to perform a process based on the data; and a distributor configured to extract the data from the data memory by referring to the pointer stored in the queue and transmit the data to the processor, wherein the distributor transmits data corresponding to a single queue to a single processor.

Apparatus and method for parallel processing

A universal virtual network function manager (VNFM) in accordance with an embodiment of the present invention includes: an orchestrator-linked interface block configured to receive a command for a virtual network function (VNF) management from a network function virtualization orchestrator (NFVO) and to analyze the command; and a VNF management block configured to manage a plurality of VNFs, each produced by a different vendor, according to the command.

Universal VNFM and method for managing VNF

An apparatus and method for managing a flow in a server virtualization environment, and a method of applying a QoS policy, the method including a flow processing unit configured to analyze a flow generated by a virtual machine (VM) to extract flow information, determine whether the flow is a new flow by comparing the extracted flow information with preset flow information, and apply a corresponding Quality of Service (QoS) policy to the flow, and a QoS management unit configured to, in a case in which the flow is a new flow, generate a QoS policy for the analyzed flow based on the extracted flow information and prestored virtual machine information, and transmit the generated QoS policy to the flow processing unit.

Apparatus and method for managing flow in server virtualization environment, and method for applying QOS

Provided are a method, apparatus, and system for providing a multi-tenant cloud service, which can guarantee quality of service (QOS) in units of flows and virtual machines (VMs). A dynamic virtual flow switch includes a switch flow agent configured to receive and store virtual machine QOS information about each of a plurality of virtual machines operating in a plurality of computer servers and flow QOS information about a flow generated by the virtual machine from a virtual flow controller and a flow processing unit configured to receive the flow generated by the virtual machine and determine a QOS priority of the flow based on the stored virtual machine QOS information of the virtual machine and flow QOS information of the flow.

Switch and method for guaranteeing quality of service of multi-tenant cloud service and system having the same switch

An apparatus includes a difference extraction unit to extract a difference between a second time stamp value, which is obtained by adjusting a first time stamp value that is measured at a time of arrival of a synchronization message transmitted by the master at a Layer 3 to be synchronized in frequency with a clock of the master, and a third time stamp value, which is measured at a time of departure of the synchronization message from the master; a minimum filter to select a minimum from one or more difference values extracted by the difference extraction unit; and a delay variation calculation unit to estimate a time of arrival of a current synchronization message at the Layer 3 based on the selected minimum and calculate a delay variation.

Apparatus and method for estimating time stamp

A parallel processing-based time synchronization apparatus employs a double-filter structure based on parallel processing, providing more precise and reliable time synchronization between a master device and a slave device. A first filter is implemented as hardware so as to realize time synchronization despite cyclic synchronization message transmission at short intervals and the second filter is implemented as software so as to realize precise time synchronization.

Time synchronization apparatus based on parallel processing

An efficient switching device and a method for fabricating the same using multiple shared memories are provided. The switching device includes: an output time determination unit to determine an output time to an output port; an output time administration unit to administer a possible data output time for each output port; a memory bank selection unit to select a memory bank with an empty data output time position; a memory bank utilization information administration unit to administer utilization information per output time; a connection unit to deliver transmission data to an output time position; a shared memory unit to store the data in the output time position, to administer dispersed shared memory banks according to an output time, and to read and output transmission data; and an output port connection unit receiving output data to read and transmit output port information of the data to a corresponding output port.

Efficient switching device and method for fabricating the same using multiple shared memories

Provided is an apparatus for changing Media Access Control (MAC) address, which is a conventional subscriber hardware identification address for identifying each subscriber, and a method thereof. The MAC address changing apparatus includes a frame receiving block for determining whether to change a source MAC address; a switch controlling block for controlling a switch; a change MAC address generating block for changing the source MAC address of the received frame; a change MAC address storing block for storing information of the change MAC address and the source MAC address corresponding thereto; a MAC address forwarding and lookup block for extracting output port information; a MAC address replacing block for forming an output frame by replacing the source MAC address; a MAC address storing block for storing a MAC address; and a frame transmitting block for transmitting the output frame.

Apparatus for changing MAC address to identify subscriber and method thereof

Provided are a method and apparatus for dynamically managing hierarchical flows that more efficiently process packet traffic while maintaining compatibility with an existing packet data network in transferring both circuit traffic and packet traffic in a packet switched network. The method for dynamically managing hierarchical flows includes: receiving data packets, classifying the data packets according to attributes of the received data packets, and producing first flows; determining whether traffic of each of the first flows exceeds a predetermined bandwidth limit, and performing a packet drop process or producing second flows for first flows that exceed the bandwidth limit, according to a flow-specific policy; and performing second flow processing on the second flows according to a second flow policy. Only flows exceeding the bandwidth limit or causing congestion are hierarchically divided for management. This makes it possible to finely manage the flows without complex operations.

Method and apparatus for dynamically managing hierarchical flows

A method for scheduling an input and output buffered ATM or packet switch and, more particularly, to a method for cell-scheduling an input and output buffered switch that is adapted to a high-speed large switch is provided. The input and output buffered switch has multiple switching planes, and its structure is used to compensated for decreasing performance of the input buffered switch resulting from HOL (head-of-line) blocking of the input buffered switch. The input and output buffered switch consists of input buffer modules grouping several input ports and output ports and output buffer modules, and each input buffer module has several FIFO queues for the associated module output buffer modules. In the input and output buffered switch having multiple switching planes, cell scheduling is carried out using a simple iterative matching (SIM) method. The SIM method consists of three operations, those are, request operation, grant operation, and accepting operation, and in the SIM method, the operations are iteratively carried out several times in one cell period, thereby matching efficiency can be increased. Each input buffered module determines simultaneously multiple FIFO queues served in one cell period, so that the SIM method with multiple selection ability has higher speed operations and better performance than conventional scheduling methods.

Cell scheduling method of input and output buffered switch using simple iterative matching algorithm

A method for using a nibble(partial bits of word) inversion code in a network system includes the steps of: a) adding 1 redundancy bit to n bit source data and generating a pre-code, n being an even number of 2 or over; b) deciding the number of transitions in the generated pre-code; c) determining the pre-code as a code word if the number of transitions in the pre-code is greater than or equal to 1&plus;n/2 in a deciding result; d) inverting alternate bits including the redundancy bit among bits constructing the pre-code and generating the code word, if the number of transitions in the pre-code is less than n/2 in the deciding result; e) determining the pre-code as the code word in case that the number of transitions in the pre-code is equal to n/2 and simultaneously the source data is not an in-band signaling and not a special word in the deciding result; and f) inverting the nibble among the bits constructing the pre-code and generating the code word, in case that the number of transitions in the pre-code is equal to n/2 and simultaneously the source data is an in-band signaling or is a special word in the deciding result.

Apparatus and method for using nibble inversion code

An nB2P coding/decoding device having a line code function facilitating data transmission and data recovery in the transmission line or link, and a function of a channel code for detecting errors in the recovered data, is provided, including: an nB2P coding device for dividing n bit width parallel data into two data units each having a predetermined bit width, and serial-transmitting the resulting n+2 bit coded data to which two odd parity bits are added, with predetermined n+2 bit with block synchronization data which is orthogonal to the coded data; and an nB2P decoding device for detecting the block synchronization data from the serially transmitted data, converts serial data to parallel form of n+2 bits, checking for errors in the coded data using the odd parity, and removing the odd parity to decode them into the original n bit width parallel data.

nB2P coding/decoding device

The present invention provides a high speed digital data retiming apparatus, in which, in binary data bits transmitted at a high speed, the data can be retimed in a stable manner, even if there are present a static skew due to a delay difference between the retiming clock pulse and the data and a dynamic skew due to the characteristic variation according to time and temperature. Therefore, the present invention has the following advantages compared with the conventional apparatus. First, periodical and regular external clock pulses are delayed by means of a delaying section, so that system performance is independent of the pattern of data. Second, even if the data phases show a continuous difference (wandering) for more than a certain period of time, an elastic buffer absorbs the wandering, and therefore, no data loss is generated, with the result that the system is not put to a disorder condition. Third, even in the case where a metastable state occurs, its occurrence probability can be significantly reduced by utilizing logic, thereby making it possible to retime the data in stable manner.

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Daejeon-si, South Korea

Bhum-Cheol Lee