Electronics and Telecommunications Research Institute

Korea Telecommunication Authority

Bheom Soon Joo

Hae Won Jung

Seok Y Kang

Min Soo Kim

Do Yeon Kim

Hyeong Ho Lee

Young Sun Kim

Bhum Cheol Lee

Jung Sik Kim

Kwon Chul Park

Bup Joong Kim

Chang Ho Choi

Tae Kyu Kang

Daeub Kim

Jae Jeong Lee

Bheom C Lee

Provided is a data processing system, including: a plurality of line matching blocks each including a data processor configured to store predefined preliminary transmission tables corresponding to the respective events requiring change of a data path, to determine whether to change a transmission table based on information received through an internal communication device, and to select and activate a preliminary transmission table corresponding to an event from among the preliminary transmission tables, wherein the preliminary transmission tables include destination information on all the physical or logical paths; and a shared bus configured to enable information on an event requiring change of the data path to be transmitted and received between the plurality of line matching blocks.

Data processing system and method for changing a transmission table

Provided are an apparatus for multiplexing Gigabit Ethernet frames and an apparatus for demultiplexing 10-Gigabit Ethernet frames. The apparatus for multiplexing Gigabit Ethernet frames includes at least one pre-processing unit, a multiplexing unit, an SDR/DDR conversion unit, and a control unit. The at least one pre-processing unit receives Gigabit Ethernet frames, converts the Gigabit Ethernet frames into 10-Gigabit Ethernet frames, and outputs the 10-Gigabit Ethernet frames. The multiplexing unit receives the 10-Gigabit Ethernet frames, time division multiplexes the 10-Gigabit Ethernet frames in frame units, and outputs the time division multiplexed 10-Gigabit Ethernet frames as first data. The SDR/DDR conversion unit, which converts the first data into second data having two 32-bit bus structures and outputs the second data. The control unit outputs a first control signal in response to an output request of the pre-processing unit.

Apparatus for multiplexing Gigabit Ethernet frame and apparatus for demultiplexing 10-Gigabit Ethernet frame

Provided is an apparatus for providing a system clock synchronized to a network universally. The apparatus includes a network synchronization reference signal generating unit that outputs a reference signal for network synchronization; a network synchronization controller that generates a first control voltage that allows a first clock pulse to be in synchronization with the reference signal for network synchronization; an OVCXO that generates the first clock pulse by application of the first control voltage; a system synchronization reference signal generator that generates reference signals for system synchronization; a system synchronization controller that generates a second control voltage that allows the system clock to be in synchronization with the reference signal for system synchronization; a VCO that generates a second clock pulse by application of the second control voltage; and a system clock generator that outputs the system clock. Accordingly, it is possible to apply to systems requiring network synchronization.

Apparatus for providing system clock synchronized to a network universally

An apparatus for managing Ethernet physical layer registers and a method thereof are provided. The apparatus comprises a central processing unit (CPU) with an external bus interface function, and an interface conversion unit which is connected to the CPU through the external bus interface, converts the external bus interface into management data input/output (MDIO) interface and performs communications with the physical layer apparatus.

Apparatus for managing Ethernet physical layer registers using external bus interface and method thereof

This invention relates to an apparatus for retiming digital data transmitted at a high speed even though the phase of a binary data bit is not related to the phase of the static offset of a retiming clock pulse, the apparatus comprising: local clock pulse generation means 11 for generating and outputting local clock pulse FT; delayed clock pulse parallel generation means 12 for outputting, in parallel, n delayed clock pulses delayed sequentially by one cycle of local clock pulse FT; input data transition detection means 13 for outputting pulse DT each time the rising and falling carrier waves intersect in input data D; sequential logic parallel phase detection means 14 for providing clock pulse selection data by outputting sequential logic phases of the upper location of the pulse generated during input data transition and transition location of n delayed clock pulses; retiming clock pulse selection means 15 for outputting a retiming clock pulse according to the clock pulse selection data of the input delayed clock pulses; time delay compensation means 16 for outputting delayed input data; and data retiming means 17 for outputting the data retimed DR according to the retiming clock pulse.

Apparatus for retiming digital data transmitted at a high speed

A high-speed bit synchronizer comprising a phase comparator for detecting a phase relationship between a center of an eye pattern of input NRZ data and a rising transition of a clock pulse from a voltage controlled oscillator (VCO) whenever the input NRZ data makes a transition, a frequency comparator for detecting a frequency relationship between a multiple of a period of the clock pulse from the VCO and a multiple of a period of an external reference clock pulse whenever the external reference clock pulse makes a rising or falling transition, phase and frequency comparator gain limiters for limiting gains of the phase and frequency comparators, respectively, a frequency synchronous signal detector for generating frequency synchronous and asynchronous signals in response to an output of the frequency comparator, a phase difference output controller for controlling the transfer of an output of the phase comparator gain limiter in response to an output of the frequency synchronous signal detector, a low pass filter (integrator) for outputting a voltage of a low frequency component to the VCO in response to an output of the phase difference output controller and an output of the frequency comparator gain limiter, and a frequency-divider for frequency-dividing the clock pulse from the VCO at a desired ratio.

High-speed bit synchronizer with multi-stage control structure

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Daejeon, South Korea

Bheom Soon Joo