Intel Corporation

Bhavya K Daya

Alexey Suprun

Kermin ChoFleming

Krishna N Vinod

Ping Zou

Sujoyita Kaushikkar

Aniket S Kakade

Systems, methods, and apparatuses relating to arbitration among a plurality of memory interface circuits in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator (CSA) includes a plurality of processing elements; a plurality of request address file (RAF) circuits, and a circuit switched interconnect network between the plurality of processing elements and the RAF circuits. As a dataflow architecture, embodiments of CSA have a unique memory architecture where memory accesses are decoupled into an explicit request and response phase allowing pipelining through memory. Certain embodiments herein provide for improved memory sub-system design via arbitration and the improvements to arbitration discussed herein.

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Hillsboro, OR, United States of America

Bhavya K Daya