Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Bhavin Odedara

Deepak Pancholi

Nitin Kumar Gupta

Srikanth Bojja

Jayanth Mysore Thimmaiah

Srinivasa Rao Sabbineni

Jayaprakash Naradasi

Naidu Prasad

Krishnamurthy Dhakshinamurthy

Rampraveen Somasundaram

Raghu Voleti

Yosi Pinto

Narendhiran Chinnaanangur Ravimohan

Anand Venkitachalam

Shajith Musaliar Sirajudeen

Sitaram Banda

Anand Sharma

Rohit Reddy

Voleti Siva Raghu Ram

Vishal Rustagi

Pikul Sarkar

Anil Kumar Thadi Suryaprakash

Ajay Dhingra

Aspects of a storage device are provided for producing an oscillator clock from a host reference clock in a storage device lacking a crystal oscillator. The storage device includes a memory die, and an oscillator circuit that generates a clock based on a host reference clock and outputs an output clock to the memory die. While the host reference clock is available, the output clock includes a frequency that is identical to a frequency or a frequency division factor of the host reference clock. In response to loss of the host reference clock, the oscillator circuit reduces the frequency of the output clock to a frequency of the generated clock within a clock cycle following the loss of the host reference clock. In response to re-availability of the host reference clock, the oscillator circuit increases the frequency of the output clock back to the frequency of the host reference clock.

SSD with reference clock loss tolerant oscillator

Systems and methods for power distribution are disclosed. A system includes a first power domain that supplies current to an integrated circuit at a first voltage level, a second power domain that supplies current to the integrated circuit at a second voltage level, and a current distribution component that is connected to the first power domain and connectable to the second power domain and senses a metric comprising a first current level or a first voltage level drawn from the first power domain, determines whether the metric exceeds a first threshold, and in response to determining that the metric exceeds the first threshold, electrically connects the second power domain to the integrated circuit to supply additional current such that an aggregate current level received by the integrated circuit comprises current from the first power domain and the additional current from the second power domain.

Current distribution from different power sources

A clock retiming circuit and method of operating a clock retiming circuit are described herein. A clock retiming circuit generates a retimed clock based on an input clock. The clock retiming circuit may have a normal mode when the input clock is available to the clock retiming circuit, and a retention mode that is entered in response to the input clock no longer being present. The clock retiming circuit resumes the normal mode in response to the clock again being present. The retention mode is a low current mode, in one aspect. Thus, the clock retiming circuit may operate in a low current mode when the input clock is not available. The clock retiming circuit may be tolerant to loss of the input clock. The clock retiming circuit may quickly re-establish the retimed clock in response to the input clock again becoming available.

Clock retiming circuit

A clock generation circuit includes a delay chain configured to generate an N-number of clock signals at a frequency multiple that is M-times the frequency of a reference clock signal. To generate the clock signals at the frequency multiple, a multiplexer selectively inputs, to the delay chain, a delayed reference clock signal and a last clock signal generated by a last delay cell of the delay chain. In addition, a delay control generator circuit periodically compares the phases of the delayed reference clock signal and the last clock signal to set the delay of the delay chain. The clock generation circuit generates the N-number of clock signals at the frequency multiple in response to receipt of the reference clock signal, and continues to generate the clock signals at the frequency multiple when the reference clock signal is no longer being received.

External clock based clock generator

A temperature identification system may include temperature sensing circuitry and a temperature measurement module. The temperature sensing circuitry may include a ring oscillator that generates a ring oscillator output signal having a frequency that varies depending on an operating temperature on the ring oscillator. A frequency divider circuit may divide the frequency of the ring oscillator output signal such that two or more cycles of a noise component of supply voltage are averaged, which may reduce the impact that the noise has on the frequency of the ring oscillator output signal. In some embodiments, a regulator may supply a regulated voltage to the ring oscillator. The regulator may reduce the impact of the noise for low frequency components of the noise, while the frequency divider may reduce the impact for high frequency of the noise.

Ring oscillators for temperature detection in wideband supply noise environments

An apparatus includes a circuit and a voltage regulator having a first output terminal that is coupled to provide electrical power to the circuit. The voltage regulator is configured to provide the electrical power in a supply voltage range. The voltage regulator has a second output terminal configured to provide an indicator of electrical current provided by the first output terminal for control of the circuit.

Dynamic distributed power control circuits

A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. The clock-sending device may delay its internal clock signal by an amount based on the one or more data signals. The clock-sending device may then perform sampling of data signals received from the clock-receiving device based on the tuning operation. The tuning operation may be performed in accordance with SDR or DDR, and thus allow for SDR or DDR communication with optimal sampling for systems that do not use a data strobe.

Tuning circuitry and operations for non-source-synchronous systems

Regulator circuitry may include a plurality of output circuits to generate a plurality of regulated output voltages. The regulator circuitry may include a single operational amplifier and a single feedback loop for regulation, which may reduce space and power consumed by the regulator circuitry. A transconductor and current mirror circuitry may be included to generate the plurality of regulated output voltages based a single operational amplifier output voltage generated with the single operational amplifier and feedback loop.

Space and power-saving multiple output regulation circuitry

A non-volatile memory system may include detection circuitry configured to detect that a host system is configured to initially communicate a clock signal and initialization command signals at a voltage level lower than its input/output driver circuit is configured to receive the signals. In response to the detection, the detection circuitry may switch a regulator circuit from a high voltage mode to a low voltage mode so that the input/output driver circuit is ready to receive the initialization commands at the lower voltage level.

Low voltage detection and initialization for non-volatile memory systems

An electronic device may receive a supply voltage from another external device, and detect when a level of the supply voltage drops below a threshold. In response, a controller of the electronic device may deactivate an interface configured for communication with the other electronic device. The controller may manage time periods and time period counters to determine when the check whether to reactivate the interface or conclude that the other external device is non-compliant.

Device soft-start management for enumeration problems with USB hosts

A buck power converter creates a desired output voltage from a greater input voltage with higher efficiency than linear regulators or charge pumps. For compact-size and cost sensitive products, the use of the buck power converter is hindered mainly because of lack of physical space and increases in the cost of the passive components like the inductor and capacitor. Techniques are presented to reduce the sizes of the passive components so that they can be integrated on-chip or in-package or on board. A signal converter in the buck power converter determines the duty cycle of a switching control signal. The switching control signal would ordinarily have driven a power switching circuit that provides current to the inductor in the buck power converter. The signal converter outputs a modified (multiphase) switching control signal that includes multiple separated on-periods that taken together approximate the duty cycle of the switching control signal while maintaining the same control loop frequency. The multiphase switching signal drives the power switching circuit to provide current to the inductor during each of the multiple separated on-periods so that the output voltage ripple decreases by a factor of the number of phases in the modified switching signal. In this way, if the ripple amplitude is kept same, the sizes of the passive components can be reduced by the factor of the number of phases in the modified switching control signal.

Multiphase low LC buck regulator

A method for calibrating an oscillator in an electronic device and an electronic device configured for calibration are provided. Multiple signals are sent to the electronic device from another electronic device, such as from a host device. With knowledge of the time interval between the multiple signals, the electronic device may calibrate the oscillator in the electronic device. For example, the electronic device may be a USB-compliant electronic device. The USB-compliant electronic device may receive Start of Frame (SoF) signals from a host device, which in one USB implementation is received at 1 mSec intervals. The USB-compliant electronic device may count the output of the oscillator between receipt of different SoF signals in order to determine the frequency of the oscillator at different oscillator settings.

System and method for calibrating capacitor-based oscillators in crystal-less devices

A method and device for calibrating an oscillator and a temperature sensor in an electronic device are provided. A same temperature cycle, which includes at least two distinct temperatures, may be used to obtain data to calibrate both the oscillator and the temperature sensor. One of the distinct temperatures may comprise an ambient temperature, and a second distinct temperature may comprise a heated temperature greater than the ambient temperature. The electronic device (or a calibration device separate from the electronic device) may receive the readings from the oscillator and the temperature sensor at the two distinct temperatures in the same temperature cycle, and may determine an oscillator correction factor and a temperature sensor correction factor.

System and method for process and temperature calibration of capacitor-based oscillators

A controlled start-up circuit mechanism in a linear voltage regulator can handle a higher supply voltage at start-up and limits the voltage seen at the devices to be lower than the maximum allowed operation voltage. The circuit may regulate voltage for operating a device coupled to a host when the host supply exceeds that necessary for device operation. The controlled start-up mechanism handles a sudden ramp up or spike of supply voltage relative to the device's operational voltage.

Controlled start-up of a linear voltage regulator where input supply voltage is higher than device operational voltage

Tuning circuitry may include a controller that is configured to determine a phase difference for a pair of signals generated at different points in a master delay line of a master-slave delay locked loop (DLL) circuit. One of signals of the pair may be communicated through a slave delay line of the master-slave DLL circuit before the phase difference is determined. A programming delay value used to set a phase delay of the slave delay line may be adjusted or tuned based on the phase difference.

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Bengaluru, India

Bhavin Odedara