Dell Products Inc.

Bhavesh Govindbhai Patel

Bhyrav M Mutnury

Timothy Michael Lambert

Mukund Purshottam Khatri

Elie Antoun Jreij

Arun Reddy Chada

Sandor Tibor Farkas

Kevin Warren Mundt

John S Harwood

Akkiah Choudary Maddukuri

Lei Wang

Mark A Muccini

Mehran Mirjafari

Robert Talbott Stevens, Iv

Wei Zhu Chen

Marshal F Savage

Indrani Paul

John J Breen

Lee Eric Ballard

Walter R Carver

Daniel Alvarado

Scott Michael Ramsey

Richard Daniel Trotta

Aubrey K Sparkman

Wallace Huson Ables

Darrell J Slupek

Douglas Simon Haunsperger

Hector F Martinez

Larry P Robison, Jr

Embodiments of systems and methods for intelligent accelerator license management are described. In some embodiments, a High Performance Computing (HPC) platform may include: a first Baseboard Management Controller (BMC), and a hardware accelerator comprising a second BMC, where at least one of the first or second BMCs is configured to: identify a type of a workload to be executed, at least in part, by the hardware accelerator, and retrieve a license corresponding to the workload.

Intelligent accelerator license management

Systems provide a chassis that support interchangeable hardware accelerator baseboards. The geometry of a first accelerator baseboard tray corresponds to the geometry of a first accelerator baseboard. The geometry of a second accelerator baseboard tray corresponds to the geometry of a second accelerator baseboard. A chassis incudes an accelerator baseboard compartment that includes a plurality of structures mounted on its base, where these structures receive corresponding structures of the first tray and that also receive corresponding structures of the second tray. Installation of the first tray on the structures mounted on the base of the compartment and installation of the first accelerator baseboard on the first tray aligns the first accelerator baseboard within the compartment. Installation of the second tray on the structures mounted on the base of the compartment and installation of the second accelerator baseboard on the second tray aligns the second accelerator baseboard within the compartment.

Chassis supporting interchangeable accelerator baseboards

An information handling system includes an enhanced networking interface, a first processor comprising a first memory device, and a second processor comprising a second memory device, wherein the enhanced networking interface is programmed to: obtain data to be processed, perform a data sharding analysis to identify the second memory device, and store, based on the identifying, the data in the second memory device.

System and method for a local level data sharding analysis of information handling systems

Embodiments of systems and methods for power throttling of High Performance Computing (HPC) components are described. In some embodiments, an HPC platform may include: a system Baseboard Management Controller (BMC), and an accelerator tray comprising a tray BMC coupled to a plurality of managed subsystems and to the system BMC, where the system BMC is configured to: in response to a power excursion event, instruct the tray BMC to throttle a first managed subsystem by a first amount and to throttle a second managed subsystem by a second amount.

Power throttling of high performance computing (HPC) platform components

Systems and methods provide management of PCIe bandwidth within an IHS (Information Handling System) through predictive evaluation of signaling degradation in PCIe lanes of the IHS. Upon initialization of the IHS, a DPU (Data Processing Unit) generates baseline signal integrity measurements for PCIe links supported by a PCIe interface of the DPU. A signaling analytic model operated by the DPU is calibrated using the baseline signal integrity measurements. A signal degradation prediction is generated by the signaling analytics model. When the signal degradation prediction is confirmed versus observed degradation in the PCIe interface, use of the signaling analytics model is activated. The activated signaling analytics module is then utilized to predict a signaling degradation in a connection supported by the PCIe interface of the DPU. In response to the prediction by the activated signaling analytics model, a corrective operation is initiated in order to prevent the predicted signaling degradation.

Systems and methods for predictive signaling analytics in high-speed data links

Systems and methods for rack-based management of leaks in liquid cooled Information Handling Systems (IHSs) are described. In an illustrative, non-limiting embodiment, an IHS configured as head node of a rack may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: receive an indication of a leak from a compute node; identify a location of the compute node in the rack; and respond to the indication based, at least in part, upon the location.

Rack-based management of leaks in liquid cooled information handling systems

Systems and methods are provided for management of PCIe bandwidth within an IHS (Information Handling System). A PCIe connection is detected between a first of the processors of the IHS and a solid-state drive accessed via a DPU (Data Processing Unit). In a processor core of the DPU (e.g., ARM core) buffers are initialized for tracking specific types of errors in the PCIe connection. Upon detecting an error in the PCIe connection, the error is added to one of the designated buffers based on a type of the detected error. If adding of the error in the PCIe connection to the buffer results in a size limit of the buffer being reached, and if the size of the buffer cannot be reduced through retransmission of the errors in the buffer, a transmission speed of the PCIe connection is downgraded, thus extending operations at higher transmission speeds.

Systems and methods for managing high-speed data links

Systems are provided where a chassis houses an Information Handling System (IHS). The chassis includes a motherboard with one or more CPUs configured to operate as a root complex for a PCIe switch fabric that includes a plurality of PCIe devices of the IHS. The chassis also includes an I/O module providing I/O capabilities for the motherboard. The I/O module includes a network controller configured to allocate network bandwidth for use by a hardware accelerator sled installed in the chassis, unless an integrated network controller is detected as a component of a hardware accelerator baseboard installed in the hardware accelerator sled. The I/O module also includes a PCI switch configured to operate with the CPUs as the root complex of the PCIe switch fabric and further configured to operate with the hardware accelerator baseboard as the root complex of the PCIe switch fabric.

Configurable chassis supporting replaceable hardware accelerator baseboards

Embodiments of systems and methods for high-availability (HA) management networks for High Performance Computing (HPC) platforms are described. In some embodiments, an HPC platform may include a first Baseboard Management Controller (BMC) having a first network port; and a hardware accelerator comprising a second BMC having a second network port, where at least one of: (a) the first BMC is configured to share the first network port with the second BMC in response to a determination that the second network port has failed or has insufficient bandwidth, or (b) the second BMC is configured to share the second network port with the first BMC in response to a determination that the first network port has failed or has insufficient bandwidth.

High-availability (HA) management networks for high performance computing platforms

Methods and systems are provided for designing an optimized stack up of layers of a PCB (Printed Circuit Board). A set of constraints is determined for the PCB stack up, where the constraints limit a total number of layers, a number of signal layers, and a thickness of the PCB stack up. Each of the constraints on the PCB stack up is encoded as an equality or an inequality. The set of equalities and inequalities is solved using integer programming techniques to identify an optimal solution to the set of constraints on the PCB stack up, where the optimal solution specifies an arrangement of signaling layers for the PCB. An estimate is generated for impedances and losses for the optimal PCB stack up. The constraints on a PCB stack up are modified when the estimated impedances and losses for the optimal PCB stack up are above a target threshold.

Systems and methods for generating PCB (printed circuit board) designs

Embodiments of systems and methods for inter-Baseboard Management Controller (BMC) integration for High Performance Computing (HPC) platforms are described. In some embodiments, an HPC platform may include a first BMC coupled to a host processor; and a hardware accelerator comprising: (a) one or more managed subsystems coupled to the host processor, and (b) a second BMC coupled to the one or more managed subsystems and decoupled from the host processor, wherein the first BMC and the second BMC are coupled to each other via a high-speed, Out-of-Band (OOB) management link.

Inter-baseboard management controller (BMC) integration for high performance computing platforms

A system for managing storage of data in a information handling systems includes a first information handling system, and a specialized information handling system comprising an enhanced networking interface, wherein the enhanced networking interface is programmed to: obtain data to be processed by the system, perform a data sharding analysis using telemetry data to identify the first information handling system, and transmit the data to the first information handling system based on the identifying.

System and method for a system level data sharding analysis of information handling systems

Systems and methods for configurable voltage regulator (VR) controllers. In some embodiments, an Information Handling System (IHS) may include: a processor; and a voltage regulator (VR) coupled to the processor, the VR configured to: identify, via a VR controller, a number of phases coupled to the voltage regulator in response to detection of a power-on-reset event; and select, via the VR controller, one of a plurality of different configuration files to be applied to the voltage regulator in response to the identification.

Configurable voltage regulator controllers

In one or more embodiments, one or more systems, methods, and/or processes may determine an engagement of a power supply unit with at least one of an information handling system (IHS) and a chassis configured to house multiple information handling systems (IHSs); may provide a power at a first voltage to the at least one of the IHS and the chassis; may determine if the at least one of the IHS and the chassis utilizes a second voltage; if the at least one of the IHS and the chassis utilizes the second voltage, may determine if the power supply unit is configured to provide the power at the second voltage; and if the power supply unit is configured to provide the power at the second voltage, may provide the power at the second voltage to the at least one of the IHS and the chassis.

Growing community of inventors

Austin, TX, United States of America

Bhavesh Govindbhai Patel