Sandisk Technologies Inc.

Bhavadip Bipinbhai Solanki

Pawan Negi

Meer Afroz Mohammed

Shreejith Koruvailu Vishwanath

Gopu S

Ganapati Bhat

Subin Cp

When an open block of NAND memory is read, this places the edge word lines under a set of bias conditions that can lead to disturbs. When time tag values are stored on predefined word lines, and the predefined word line is an edge word line, this can degrade not just the user data on the word line, but also the time tag values, leading to a failed bit count spike. To address this problem, a time tag word line shift approach is introduced where, if a predetermined time tag acquisition word line is an edge word line, another word line is instead used to acquire the time tag value.

Time tag word line shift to reduce failed bit count spikes for edge word lines

A memory device includes a wordline zone table that stores information about how wordlines of one or more memory blocks are divided into wordline zones. The wordline zone table also stores a value associated with each wordline zone. When the memory device receives a command, a controller identifies a wordline associated with the command. The controller uses the wordline zone table to determine the wordline zone, and the value, associated with the wordline. The value is stored in a non-data wordline. When a find last good page (FLGP) process is initiated in response to an ungraceful device shutdown (UGDS) event, the controller determines the value stored in the non-data wordline. The controller compares the value in the non-data wordline to the values in the wordline zone table to determine which wordline zone matches the value. The FLPG process is applied to the wordline zone having the matching value.

Using a zone wordline table to initiate a find last good page process

A data storage device can check data integrity on a wordline in memory each time the data storage device exits a low-power mode. Frequent exits from the low-power mode result in the wordline being read many times, which can result in a read disturb problem. To mitigate this problem, in one embodiment disclosed herein, a different wordline is used to check data integrity each time of a plurality of times that the data storage device exits a low-power mode. Using different wordlines for the data integrity check can reduce the likelihood of a read disturb error. Other embodiments are disclosed.

Data storage device and method for read disturb mitigation during low-power modes

Different pages of a quad-level cell (QLC) memory can have different data retention characteristics. A controller of a data storage device can store selected data in relatively-lower data retention pages of the QLC block. For example, data for an internal data storage device operation can be stored in the relatively-lower data retention pages of QLC memory, and host data can be stored in the relatively-higher data retention pages of QLC memory. Other examples are provided.

Data storage device and method for storing selected data in relatively-lower data retention pages of a quad-level cell memory

A non-volatile storage system comprises a group of non-volatile memory cells, and one or more control circuits in communication with the group. The one or more control circuits are configured to perform a plurality of passes to revise a read reference signal based on comparisons of numbers of non-volatile memory cells in the group having a value for a physical property (e.g., threshold voltage or resistance) in adjacent regions. With each pass the adjacent regions are smaller. The one or more control circuits are configured to establish a final read reference signal based on a signal associated with one of the adjacent regions on a final pass of the plurality of passes. The one or more control circuits are configured to use the final read reference signal to distinguish between two adjacent data states stored in the group.

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Bengaluru, India

Bhavadip Bipinbhai Solanki