Avago Technologies International Sales Pte. Limited

Bhaswar Mitra

Chi Ho Fredrek Choi

Amit Narayan Gupta

Arun Prasath Chandrasekaran

Mark Birman

Nitin Vinay Isloorkar

In some aspects, the disclosure is directed to methods and systems for a flexible type-length-value (TLV) parser and identification map that may be used to quickly identify TLV sequences of packet headers for subsequent processing in a pipeline. A flexible TLV bus may provide a secondary path for the TLV header and identification map, allowing for subsequent processing stages to read, process, modify, delete, or otherwise utilize individual TLV sequences within the header.

Efficient TLV style header parsing and editing

A system including memory, a lookup circuit and an address circuit. The memory can store a plurality of tables. Each table can have a plurality of entries and each entry can have an entry index. The lookup circuit can be coupled with the memory. The lookup circuit can provide the plurality of entry indexes of the plurality of tables to the address circuit. The address circuit can include a first circuit, a second circuit, and third circuit. The first circuit can include a plurality of entry scramblers. The second circuit can include a plurality of translators, and the third circuit can include a plurality of row scramblers.

Systems and methods for address scrambling

Described herein are a device and a method for performing a network analysis. In one aspect, the device includes a feature extraction circuit, an input processing circuit, and a reconfigurable neural network circuit. In one aspect, the feature extraction circuit receives a raw packet stream, and obtains temporal statistics of a flow, according to a first packet attribute or a first flow attribute of the raw packet stream. In one aspect, the feature extraction circuit generates a feature data including one or more statistical features based on the temporal statistics of the flow. In one aspect, the input processing circuit scales the feature data to generate an adjusted feature data. In one aspect, the reconfigurable neural network circuit performs computations corresponding to a neural network on the adjusted feature data to determine a predicted network characteristic.

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Santa Clara, CA, United States of America

Bhaswar Mitra