National Semiconductor Corporation

Bhaskar V Gadepally

Sheldon Aronowitz

George P Walker

Farrokh Mohammadi

Donald D Forsythe

Peter P Meng

Body to drain junction breakdown, due to avalanching in DMOST devices, can be controlled. The invention lowers the electric field gradients in the vicinity of the PN junction. The structure employed to enhance breakdown behavior is specifically applied to a vertical DMOST. The N type doping profile in the vicinity of the body to drain junction is tailored by constructing a P-nu-N-N.sup.+ type diode structure where nu is a low N type impurity concentration region. The N type region is of higher impurity concentration and is more extensive. With the nu region having one-half of the impurity concentration of the N region and an extent of about two microns, the avalanche breakdown voltage is about 27% higher than the conventional PN junction diode. By making the nu region impurity concentration one-fourth that of the N region, the breakdown voltage is 40% higher.

Dmost junction breakdown enhancement

A semiconductor memory device having a CMOS memory cell with a floating gate and increasing concentration of dopant in the source, drain and channel regions. Typically the concentration profile is generally exponential across the channel width. The device has relatively high diffusion current densities accelerated toward the surface and directed toward the channel/drain interface. Gate oxidation thickness is reduced over the channel near the drain to create a tunnel 'window' in the area of greatest electric field magnitude. The device provides for significantly reduced write times as compared to conventional devices.

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San Jose, CA, United States of America

Bhaskar V Gadepally