International Business Machines Corporation

Bhaskar Sinha

Casper A Scalzi

Balakrishna Raghavendra Iyer

Kenneth E Plambeck

Richard I Baum

Carl Edward Clark

Teresa A Meriwether

Inderpal Singh Narang

Michael Gerard Mall

Elton B Sherwin, Jr

Gururaj Seshagiri Rao

Hatem Mohamed Ghafir

Moon Jung Kim

Jeffrey Alan Frey

Satya Prakash Sharma

Brent Allen Carlson

Kathryn Marie Jackson

Glen A Brent

Joseph M Gdaniec

Richard J Schmalz

Peter H Gum

Lee Hardy Wilson

Alan I Alpert

James G Brenza

Richard J Schmalz, Deceased

Michel Henri Hack

Mark M Maccabee

Gururaj S Rao

Clark Kurtz

Chi-Hung Chi

Hatem M Ghafir

Lee H Wilson

A method for obtaining parallel instruction execution (PIE) for frequently used programming operations, such as database record compression or expansion, cryptographic encoding/decoding, page moving, etc., for which a hardware-assist may be provided. These functions can be performed in parallel with CPU processing by a PIE processing facility (PIE-PF). The method is hardware/microcode based and uses software control in supervisory mode. The preferred embodiment is controlled by privileged subsystem software under an operating system, and does not use I/O channel oriented off-load processing. When the CPU is interrupted during an incomplete parallel operation by the PIE-PF, it is checkpointed in main storage in a manner accessible to the subsystem. The subsystem (after completing a current CPU operation, such as a database record predicate evaluation, can check for the completion of the PIE-PF operation by examining an indicator in a control block in shared storage. Furthermore, if the parallel operation has not completed, the CPU can: a) continue the PIE-PF processing in parallel with other processing in the CPU, b) halt the parallel PIE-PF asynchronous operation and have the CPU do the rest of the operation synchronously, or c) resume the parallel operation in the processor or a hardware assist if an interruption caused the PIE-PF parallel operation to be checkpointed.

Method for a CPU to utilize a parallel instruction execution processing

A coexecutor for executing functions offloaded from central processors (CPs) in a data processing system, as requested by one or more executing control programs, which include a host operating system (host OS), and subsystem programs and applications executing under the host OS. The offloaded functions are embodied in code modules. Code modules execute in the coexecutor in parallel with non-offloaded functions being executed by the CPs. Thus, the CPs do not need to execute functions which can be executed by the coexecutor. CP requests to the coexecutor specify the code modules which are accessed by the coexecutor from host shared storage under the same constraints and access limitations as the control programs. The coexecutor may emulate host dynamic address translation, and may use a provided host storage key in accessing host storage. The restricted access operating state for the coexecutor maintains data integrity. Coexecutors can be of the same architecture or of a totally different architecture from the CPs to provide an efficient processing environment for the offloaded functions. The coexecutor interfaces host software which provides the requests to the coexecutor. Offloaded modules, once accessed by the coexecutor, may be cached in coexecutor local storage for use by future requests to allow subsequent invocations to proceed without waiting to again load the same module.

Coexecution processor isolation using an isolation process or having

Provides a dynamic execution link between an analyzer program and each hook instruction in a program. Special types of hook instructions are provided for use in a hooked program. The link causes the analyzer program to execute as part of a continuous uninterrupted execution for each hook instruction. The link uses hardware and/or internal code to access a hook control area which provides linkage information needed to invoke the execution of the analyzer program upon completion of the hook instruction and to continue the execution of the hooked program following the completion of the analyzer program. The linkage information includes the entry location into the analyzer program, and also locates the first hook work area (HWA) of a sequence of HWAs, from which an HWA is assigned to each current hook instruction. The assigned HWA stores a return point location in the hooked program at an instruction following the current hook instruction. One or more hooked programs may concurrently use the same analyzer program. As soon as execution by the analyzer program ends for a hook instruction, its assigned HWA is released for use by another hook instruction.

Dynamic program analyzer facility

Ziv-Lempel-type compression and expansion using separate static compression and expansion dictionaries as opposed to a single adaptive dictionary. The static dictionaries make random access processes usable for short data records instead of only long sequential data streams. Degree of compression and compression performance are improved by allowance of multiple extension characters per node and multiple children, of the same parent, that have the same first extension character. Performance is further improved by searching for matches on children of a parent and detecting a last possible match by means of fields in the parent instead of by accessing the children. Expansion performance is improved by representing in an entry not only the extension character or characters of the entry but also those of some number of ancestors of the entry, thus avoiding accessing the ancestors.

Method and means providing static dictionary structures for compressing

An addressing method using large addresses in a guest/host environment within a computer system. The guests are operating-systems, and the host is a hypervisor program. Each guest has a guest real address space (guest RAS) mapped onto a host large real address space (host LRAS) using means disclosed herein. To do this, each guest RAS is first assigned to a contiguous part of a host large virtual address space (LVAS) by assigning each guest RAS to one or more contiguous units of virtual addressing in the host LVAS, each unit having a 2 gigabyte (GB) size. The host LVAS is represented by a sequence of entries (ALEs) in a host access list (AL), in which each ALE represents a 2 GB unit of virtual addressing in the host LVAS. An ALE is selected in the AL by using a high-order part of a host large virtual address (host LVA) representing a guest RA or LRA. A host LVA is generated from a guest RA for obtaining the guest address in host main storage. The host LVA is translated in a number of different ways to a host LRA, depending on the type of guest providing the corresponding guest RA or LRA. The guest types include V=V, V=FC, V=FD and V=R guests, which is indicated in a guest control block (GCB).

Guest/host extended addressing method and means with contiguous access

Describes novel methods for compressing data character strings into 'storage optimized indices' (SOIs) and stores their adaptive Ziv Lempel (AZL) indices, called 'evolution based indices' (EBIs), in fields in corresponding entries in a SOI dictionary. The method also compresses data using the SOI dictionary, which accesses the corresponding EBIs for representing the compressed data. The EBIs are put into storage, or transmitted to a receiving location. Greater data compression processing efficiency is obtained by using the SOI dictionary than is available using prior types of AZL dictionaries. The disclosure further describes methods for decompressing EBI indices into corresponding phrases at a receiving location using either a conventional AZL dictionary or a SOI dictionary after translating received EBIs into SOIs. Also described is a submethod for phrase length determination for use in the decompression process. Using this phrase length detection, received phrases are decompressed in their reverse character order through a buffer, or directly in a target storage area, or in a combination of the latter two techniques. The phrase length may be stored in corresponding dictionary entries to avoid a length tracing process in the invention.

Transmission compatibility using custom compression method and hardware

Allows instructions and data to be located in any one or more of plural sections of a large-size real memory of a data processing system. Any memory section is located by concatenating a conventional small real/absolute address with an address extender used with conventional small-size memory. A Central Processor Extended Address Mode (CPEAM) register content indicates the location of extenders in an AR(s), ASTE(s), STE(s) or PTE(s) for use by a central processor or I/O operations. An Input-Output Extended Address Mode (IOEAM) register content indicates the location of the extenders in ORB(s), CCW(s) or IDAW(s) for use by I/O operations. A compatible mode sets the content to zero for either or both of the CPEAM and IOEAM if either or both is not to be used.

System for addressing a very large memory with real or virtual addresses

A method and apparatus for translating a large logical address as a large virtual address (LVA) when a dynamic address translation (DAT) mode is on. Each LVA is separated into three concatenated parts: 1. a highest-order part (ADEN) for indexing into an access directory (AD) to locate an entry (ADE) for locating one access list (AL); 2. an intermediate part (ALEN) for indexing into a selected AL to access an entry (ALE) that enables location of an associated conventional address translation table which represents a conventional size virtual address space; and 3. a low-order DAT virtual address (VA) part having the same size as a conventional type of virtual address. The low-order DAT VA part is translated by the associated conventional address translation table. If a carry signal is generated during the creation of the low-order DAT VA part, then a change in the selection of an ALE results. An offset value of ALEs can be utilized to generate an effective ADEN and ALEN, which are utilized for the address translation of the LVA.

Large logical addressing method and means

A Branch in Subspace Group (BSG) instruction is executed in problem state (for example by an application program) for providing a fast instruction branch between address spaces within a restricted group of address spaces called a subspace group. The subspace group contains two types of address spaces: a base space and any number of subspaces. The subspace group is set up in a control table associated with each dispatchable unit (DU). This DU control table contains: an identifier of a base space, an identifier of an access list that contains identifiers of all subspaces in the subspace group, an indicator of whether CPU control was last given to a subspace or to the base space, and an identifier of a last entered subspace in the group. The BSG instruction has an operand defining a general register containing the target virtual address and an associated access register containing an access-list-entry token (ALET) defining the target address space. The ALET indexes to a target subspace identifier in the access list, and then the associated virtual address locates the target instruction in the identified target address space. BSG instruction execution controls restrict the BSG branching only to an instruction in the subspace group.

Storage isolation with subspace-group facility

Improvements are made to standard run length encoding compression techniques to permit frequently occurring repeated bytes to be dynamically redefined or reset to a default value such as a blank character, repeated multiple byte units or strings to be more efficiently coded and run length encoded enhancements allow compression of data where characters are represented by multiple bytes. The Sequence Control Byte (SCB) is modified to communicate indications to a receiver that the compression mode of 1 to N bytes per character is being changed and to indicate what the change is or that a con, non master repeat character frequently encountered in data is being redefined to be another character or that characters are going to be encoded in multiple bytes. The SCB format which is well known in the prior art is modified to include specific bit patterns or codes in the first two bits of the SCB byte to indicate setting of the bytes per character encoding mode to a different value, resetting the encoding mode to a default value or redefining a commonly repeated character or defining a character to be multiple bytes or a string of characters which may be multiple byte characters. The other six bits of the SCB are assigned code values unused in the prior art to indicate the number of tines that a defined character is to be repeated, whether a master character that has been defined is to be repeated or whether a character string is to be repeated. Two fields of data are thus formatted in the SCB with new values to indicate to a receiver these new criteria.

Multimode and multiple character string run length encoding method and

A method of transmitting compressed data using a Ziv-Lempel compression/expansion algorithm, using an adaptive Ziv-Lempel (AZL) dictionary modified to a mature state. The mature state is signaled by a time to freeze signal sent as a switch-over signal from a transmitting location to each receiving location. These signals freeze and synchronize the AZL dictionaries at both locations, and starts a translation of the frozen AZL dictionary to a static SZL dictionary--at least at the transmitting location. The SZL dictionary is then used to compress records being transmitted. An index translation process is generates translation information to allow the receiving locations to decompress SZL indices into original characters. The AZL-to-SZL dictionary translation process re-organizes the frozen AZL to an SZL dictionary. The SZL process is used until either the end of the inputted sequence, or a time to unfreeze signal is generated. An SZL to AZL switch-over signal is generated in response to the time to unfreeze signal, which in turn signals a switch over back to the AZL process and invokes the saved frozen AZL dictionary to be used to until mature to on the current input data stream at which time the AZL is frozen and a switch-over signal is provided and a new SZL is generated.

Semi-static data compression/expansion method

Provides three access levels of storage key protection, comprising a supervisory level (key 0), an intermediate level of non-public and non-supervisory keys (keys 1-8, 10-15), and an unique public level (key 9). The program routines operating with a supervisory-level access key can access both the public level and the intermediate level of storage blocks. Although a program routine operating with an access key in the intermediary access level cannot access any supervisory level storage block, it can access any block assigned a public level storage key, as well as any storage block assigned the respective intermediate level key. One or more third-level public storage keys (PSKs) may be provided. A program access key using one of the PSK values can only access blocks having the same PSK value, and it cannot access blocks having any other key value.

Growing community of inventors

Wappingers Falls, NY, United States of America

Bhaskar Sinha