Analog Devices,inc.

Analog Devices International Unlimited Company

Analog Devices Global

Bhargav R Vyas

Roberto Sergio Matteo Maurino

Arvind Madan

Christopher Peter Hurrell

Adrian Sherry

Andrew Joseph Thomas

Sandeep Monangi

Venkata Aruna Srikanth Nittala

Kaushal Kumar Jha

Kirubakaran Ramalingam

Gerard Mora Puchalt

Mrinmay Talegaonkar

Ayesha Shaik

Chopping techniques that suppress fold-back into the signal band and spreads the offset across the spectrum are described. By using various techniques, chopping may be performed with a variable frequency clock to spread the offset across the signal spectrum. Spreading the offset across the signal spectrum means that there are no longer large spurious tones at a few frequencies.

Spread spectrum chopping for sigma delta modulators

Systems, devices, and methods related to low-noise, high-accuracy single-ended continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) are provided. An example single-ended CTSD ADC includes a pair of input nodes to receive a single-ended input signal and input circuitry. The input circuitry includes a pair of switches, each coupled to one of the pair of input nodes; and an amplifier to provide a common mode signal at a pair of first nodes, each before one of the pair of switches. The single-ended CTSD ADC further includes digital-to-analog converter (DAC) circuitry; and integrator circuitry coupled to the input circuitry and the DAC circuitry via a pair of second nodes.

Low-noise, high-accuracy single-ended input stage for continuous-time sigma delta (CTSD) analog-to-digital converter (ADC)

A multistage noise shaping (CT-MASH) converter with phase alignment is provided. The CT-MASH converter may include a prefilter, an auxiliary path with an adjustable continuous time sigma delta converter (CTSD), and a modulator. The adjustable CTSD may provide phase alignment using one or more of a variety of techniques, such as modifying a group-delay of the CTSD by tuning a feedforward coefficient, by tuning an excess loop delay coefficient, and/or by adjusting a clock timing of the CTSD.

Phase alignment of CT-MASH converter

A multichannel system, including a multiplexer having inputs for a plurality of input channels, and a pre-charge buffer having a plurality of inputs coupled to an input of the multiplexer, and an output coupled to a multiplexer output. The multichannel system may stand alone, or may be coupled to a receiving circuit having an input coupled to an output of the multiplexer. In some instances, the receiving circuit is an analog to digital converter.

Input current cancellation scheme for fast channel switching systems

Multichannel successive approximation register (SAR) analog-to-digital converters (ADC), along with methods and systems for multichannel SAR analog-to-digital conversion, are disclosed herein. An exemplary multichannel SAR ADC can include a first SAR ADC for each of a plurality of input channels, and a second SAR ADC, a multiplexer, and a residue amplifier shared among the plurality of input channels. The multiplexer can select an analog residue signal from one of the first SAR ADCs for conversion by the second SAR ADC. The residue amplifier can amplify the selected analog residue signal. The second SAR ADC, multiplexer, and/or residue amplifier may be shared among all of the plurality of input channels. Where the multichannel SAR ADC includes N input channels, the second SAR ADC, multiplexer, and/or residue amplifier may be shared among b channels of the N input channels.

Multichannel analog-to-digital converter

Techniques to compensate for sources of temperature and process dependent errors within an oscillator system for frequency control oscillator output clock signal. The oscillator system may include a controller and an oscillator circuit. The techniques may include generating a pair of voltages, a first of which is temperature variant, having (approximately) known temperature variations across process, and a second of which is (approximately) temperature invariant. Each voltage may be scaled by a corresponding trim factor. The scaled voltages may be combined to generate a reference voltage. The reference voltage may compensate for process and temperature dependent error sources within the oscillator system to set the oscillator output clock signal frequency.

System and method for oscillator frequency control

Digital potentiometer architecture is disclosed, composing of an integrated circuit containing multiple string arrays, each having a plurality of switching devices and an array of resistors. The insertion of an additional string array between the input terminals and the wiper, allows for the disconnection of a common string array and for the independent calibration of the resistance between each input terminal and the wiper.

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Bengaluru, India

Bhargav R Vyas