Skyworks Solutions, Inc.

Bharatjeet Singh Gill

Michael Joseph McPartlin

Stephen Joseph Kovacic

Grant Darcy Poulin

Mackenzie Brian Cook

Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps.

Direct substrate to solder bump connection for thermal management in flip chip amplifiers

A method of forming a flip-chip integrated circuit die that includes a front side including active circuitry formed therein and a plurality of bond pads in electrical communication with the active circuitry, at least two through-wafer vias in electrical communication with the active circuitry and extending at least partially though the die and having portions at a rear side of the die, and a bond wire external to the die and electrically coupling the portions of the at least two through-wafer vias to one another at the rear side of the die.

Backside metalization with through-wafer-via processing to allow use of high Q bond wire inductances

Examples of the disclosure include an amplifier system comprising an amplifier having an input to receive an input signal, and an output to provide an amplified output signal, the amplifier having a power level indicative of at least one of the input signal power and the amplified output signal power, and a linearizer coupled to the amplifier and having a plurality of modes of operation including a fully disabled mode and a fully enabled mode, the linearizer being configured to determine the power level of the amplifier, select a mode of operation of the plurality of modes of operation based on the power level of the amplifier, determine one or more linearization parameters corresponding to the selected mode of operation, and control linearization of the amplified output signal based on the determined one or more linearization parameters.

Auto-linearizing amplifier

A flip-chip integrated circuit die includes a front side including active circuitry formed therein and a plurality of bond pads in electrical communication with the active circuitry, at least two through-wafer vias extending at least partially though the die and having portions at a rear side of the die, and a bond wire external to the die and electrically coupling the portions of the at least two through-wafer vias at the rear side of the die.

Backside metalization with through-wafer-via processing to allow use of high q bondwire inductances

Metal pillars are placed adjacent to transistor arrays in the power amplifiers that can be used in wireless devices. By placing the metal pillars in intimate contact with the silicon substrate and not over a substantial portion of the transistor arrays, the heat generated by the transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar forms a solder bump of a flip chip power amplifier die, which when soldered to a module, further conducts the heat away from the transistor array.

Flip chip amplifier for wireless device

Metal pillars are placed adjacent to NPN transistor arrays that are used in the power amplifier for RF power generation. By placing the metal pillars in intimate contact with the silicon substrate, the heat generated by the NPN transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar also forms an electrical ground connection in close proximity to the NPN transistors to function as a grounding point for emitter ballast resistors, which form an optimum electrothermal configuration for a linear SiGe power amplifier.

Solder bump placement for thermal management in flip chip amplifiers

Solder bump placement for grounding in flip chip amplifiers

Solder bump placement for emitter-ballasting in flip chip amplifiers

Disclosed are circuits and methods related to low-noise amplifiers (LNAs) having improved linearity. In some embodiments, a radio-frequency (RF) amplifier circuit can include a first amplifying transistor configured to amplify an RF signal. The RF amplifier circuit can further include a switchable inductance circuit that couples the first amplifying transistor to a signal ground. The switchable inductance circuit can be configured to be capable of providing at least two different inductance values that yield different linearity levels for the RF amplifier circuit. A high linearity performance can be obtained with a higher inductance and a lower bias voltage, thereby reducing power consumption of the RF amplifier. Examples of methods and devices related to such an RF amplifier circuit are disclosed.

Growing community of inventors

Ottawa, Canada

Bharatjeet Singh Gill