Advanced Micro Devices Corporation

Motivo, Inc.

Other

Globalfoundries Inc.

Michigan State University

Advance Micro Devices, Inc.

Bharath Rangarajan

Bhanwar Singh

Ramkumar Subramanian

Khoi A Phan

Michael K Templeton

Sanjay K Yedur

Bryan K Choo

David Keating Foote

Fei Wang

Ursula Q Quinto

Christopher F Lyons

Steven C Avanzino

Jeffrey Allan Shields

Stephen Keetai Park

Cyrus E Tabery

Dawn M Hopper

Carmen L Morales

Steven K Park

Vito Dai

Ji Xu

Edward Kah Ching Teoh

Mark T Ramsbey

Srikanteswara Dakshina-Murthy

Mark S Chang

Allen S Yu

George Jonathan Kluth

Guarionex Morales

Kathleen R Early

Jack F Thomas

Hideki Komori

Tuan Duc Pham

Arvind Halliyal

Paul J Steffan

Iraj Emami

Alec B Scranton

Catherine B Labelle

Christy Mei-Chu Woo

Marina V Plat

Wenge Yang

Simon Siu-Sing Chan

Larry Yu Wang

Jusuke Ogura

Tim Thurgate

Kenneth W Au

Jeff Shields

Stephan Keetai Park

Cristina Cheung

Mike Templeton

Alvin M Dangca

Michael T Templeton

George Jon Kluth

Terry Manchester

Kiran K Baikerikar

Lindsay S Coons

In an embodiment, a method for optimizing an integrated circuit physical design for an integrated circuit. A physical design graph includes a plurality of physical design sub-configurations, each including a placement of a group of physical cells and having annotated characteristics. The method includes identifying, in the integrated circuit physical design, a first physical design sub-configuration including a first placement of a first group of the physical cells and having first annotated characteristics, the first annotated characteristics being outside target characteristics. The method includes selecting from the physical design graph, based on the first group of the physical cells and the target characteristics, at least a second physical design sub-configuration including a second placement of the first group of the physical cells and being within the target characteristics. The method includes replacing the first physical design sub-configuration in the integrated circuit physical design with the second physical design sub-configuration.

Optimization of physical cell placement for integrated circuits

In an embodiment, a method for designing an integrated circuit with target characteristics uses a physical design graph. The physical design graph includes a plurality of physical design sub-configurations, each of the plurality of physical design sub-configurations including a placement of a group of physical cells and having annotated characteristics. The method includes partitioning an integrated circuit electrical design into a plurality of electrical design sub-configurations, including a specific electrical design sub-configuration requiring a specific group of the physical cells. The method includes selecting from the physical design graph, based on the required specific group of the physical cells and the target characteristics, a physical design sub-configuration including the specific group of the physical cells in a specific placement and having the target characteristics. The method includes determining an integrated circuit physical design for manufacturing the integrated circuit.

And optimization of physical cell placement

Methods for integrated circuit design are provided. In one embodiment, a method for determining a physical layout pattern includes accessing a layout pattern configuration graph. The graph includes layout pattern configurations meeting a circuit requirements. At least two of the layout pattern configurations are annotated with characteristics by analyzing sample layout patterns. An integrated circuit electrical design is partitioned into circuit design configurations. One of the circuit design configurations meets one of the circuit requirements. One of the layout pattern configurations is selected from the layout pattern configuration graph to meet the selected circuit requirements. In another embodiment, a method for determining a netlist for an integrated circuit electrical design is provided. In a further embodiment, a method for determining a tool configuration for a manufacturing process is provided.

Integrated circuit design systems and methods

The present invention provides for a system and method for regulating and monitoring heat dissipation of an integrated circuit by employing a heat regulating device with a thermal structure net work assembly. Each thermal structure can act as a heat conducting pathway for inducing heat into and/or dissipating heat away from the integrated circuit, thus creating a more uniform temperature gradient across the semiconductor body.

Mitigating heat in an integrated circuit

The invention provides systems and processes that form the inverse (photographic negative) of a patterned first coating. The patterned first coating is usually provided by a resist. After the first coating is patterned, a coating of a second material is provided thereover. The uppermost layer of the second coating is removed, where appropriate, to expose the patterned first coating. The patterned first coating is subsequently removed, leaving the second coating material in the form of a pattern that is the inverse pattern of the first coating pattern. The process may be repeated with a third coating material to reproduce the pattern of the first coating in a different material. Prior to applying the second coating, the patterned first coating may be trimmed by etching, thereby reducing the feature size and producing sublithographic features. In addition to providing sublithographic features, the invention gives a simple, efficient, and high fidelity method of obtaining inverse coating patterns.

Inverse resist coating process

A mask is provided to be used with nanoprint lithography processes to facilitate reproduction of small features required for the production of integrated circuits. A translucent substrate is provided along with one or more three-dimensional features that include one or more vertical sidewalls. An absorbing material is deposited upon one or more of the vertical sidewalls so that light in an incident direction to an upper surface of the substrate will be absorbed by the absorbing material, resulting in light blocking features. One or more horizontal surfaces are formed upon one or more of the three-dimensional features, which allow light rays to exit a lower surface of the substrate unobstructed by the absorbing material.

Mask having sidewall absorbers to enable the printing of finer features in nanoprint lithography (1XMASK)

The present invention provides a system and methodology for dummy-dispensing resist though a dispense head while mitigating waste associated with the dummy-dispense process. The dummy dispensed resist is returned to a reservoir from which it was taken. Between substrate applications, the dispense head can be positioned to dispense resist into a return line. The flow of resist from the dispense head keeps resist from drying at the dispense head. By funneling the dummy-dispensed resist into a return line with low volume, for example, waste from the dummy-dispensing process can be mitigated.

Recirculation and reuse of dummy dispensed resist

A system and method are provided for detecting contaminants or defects on a reticle in-situ. The system and method provide a system that measures the optical transmission through clear areas on a reticle and determines whether the optical transmission of a reticle has been degraded by contaminants or other defects.

In-situ reticle contamination detection system at exposure wavelength

A system and method for detecting bubbles in a lithographic immersion medium and for controlling a lithographic process based at least in part on the detection of bubbles is provided. A bubble monitoring component emits an incident beam that passes through the immersion medium and is incident upon a substrate to produce a reflected and/or diffracted beam(s). The reflected and/or diffracted beam(s) is received by one or more optical detectors. The presence or absence of bubbles can be derived from information extracted by scatterometry from the reflected and/or diffracted beams. A process control component interacts with a positioning component and an optical exposure component to alter a lithographic process based at least in part on the results of the scatterometry.

In-situ defect monitor and control system for immersion medium in immersion lithography

Systems and/or methods are disclosed for aligning multiple layers of a multi-layer semiconductor device fabrication process and/or system utilizing a composite alignment mark. A component is provided to form the composite alignment mark, such that a first portion of the composite alignment mark is associated with a layer of the wafer and a second portion of the composite alignment mark is associated with a disparate layer of the wafer. An alignment component is utilized to align a reticle for a layer to be patterned to the composite alignment mark.

Composite alignment mark scheme for multi-layers in lithography

The present invention relates to visually monitoring an interior portion of a processing chamber in a semiconductor processing system. An image collector collects images of the interior of the chamber and provides an image signal indicative of a visual representation of the interior of the chamber. A viewing station receives the image signal and displays a visual representation of the interior of the chamber.

System and method for visually monitoring a semiconductor processing system

Systems and/or methods are disclosed for measuring and/or controlling an amount of impurity that is dissolved within an immersion medium employed with immersion lithography. The impurity can be photoresist from a photoresist layer coated upon a substrate surface. A known grating structure is built upon the substrate. A real time immersion medium monitoring component facilitates measuring and/or controlling the amount of impurities dissolved within the immersion medium by utilizing light scattered from the known grating structure.

Real time immersion medium control using scatterometry

Re-circulation and reuse of dummy-dispensed resist

A system and method is provided for monitoring and controlling the contaminant particle count contained in an aerosol during a photoresist coating and/or development process of a semiconductor. The monitoring system monitors the contaminate particle count present in the environment of the photoresist coating and/or development process, such as in a process chamber or a cup, enclosing the wafer during the process. The present invention employs in situ laser scattering or laser doppler anemometry techniques to detect the particle count level in the chamber or cup. A plurality of lasers and detectors can be positioned at different heights in or outside of a chamber or cup to facilitate detecting particles at different height levels. A laser could be used in conjunction with mirrors to provide a similar measurement. The particle count level can be used to compare with the defect level, so that it can be determined if a cleaner environment and/or process should be implemented.

In situ particle monitoring for defect reduction

Growing community of inventors

Santa Clara, CA, United States of America

Bharath Rangarajan