Cadence Design Systems, Inc.

Bharath Nandakumar

Krishna Chakravadhanula

Sameer Chakravarthy Chillarige

Anil Malik

Sarthak Singhal

Prateek Kumar Rai

A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that divide the test-point nodes into a plurality of test-point sharing groups in which each of the test-point nodes is associated with one of the clock-gates that is common to each of at least one flip-flop of the portion of the functional logic coupled to each of the respective test-point nodes in the test-point sharing group. The test-point flop allocation module can further allocate one of the test-point flops to each of the test-point sharing groups. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design based on the circuit netlist. The circuit layout is employable to fabricate an IC chip.

Clock-based test-point flop sharing in a circuit design

Scan channel slicing methods and systems for testing of scan chains in an integrated circuit (IC) reduce the number of test cycles needed to effectively test all the scan chains in the IC, reducing the time and cost of testing. In scan channel slicing, rather than loading and unloading into scan chains high-power patterns having numerous switching transitions over the length of each scan chain, loading and unloading the entirety of the scan chain scan while observing it, chain load data is sliced, apportioning between the different scan chains independently observable sections (slices) of transition data in which all four bit-to-bit transitions ('0' to '0', &#x201c;0&#x201d; to &#x201c;1&#x201d;, &#x201c;1&#x201d; to 0&#x201d;, &#x201c;1&#x201d; to &#x201c;1&#x201d;) are ensured to exist. The remainder of the scan chain load data, which is not observed in the test procedure, can be low-transition data that consumes low dynamic power, such as mostly zeroes or mostly ones.

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New Delhi, India

Bharath Nandakumar