Texas Instruments Corporation

Maxlinear Asia Singapore Pte Ltd

Bharath Kumar Singareddy

Suzanne Mary Vining

Win Naing Maung

Hormoz Djahanshahi

Douglas Edward Wente

Mustafa Ulvi Erdogan

Srinivasa Rao Madala

Stanley Ho

Soumi Paul

Anant Shankar Kamath

Mayank Garg

Rakesh Hariharan

Kanteti Amar

High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.

Frame-based, low power interfaces between devices with different I/O signals

A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

Data bus signal conditioner and level shifter

Methods, apparatus, systems, and articles of manufacture corresponding to a low area and high speed termination detection circuit with voltage clamping are disclosed. An example apparatus includes a transistor including a first control terminal, first current terminal and a second current terminal, the second current terminal adapted to be coupled to a load. The apparatus further includes a logic gate including an input coupled to the first current terminal. The apparatus further includes a current source including a second control terminal, a third current terminal coupled to a voltage rail and a fourth current terminal coupled to the first current terminal and the input of the logic gate.

Low area and high speed termination detection circuit with voltage clamping

Method and systems are provided for voltage-controlling and tuning of oscillators. An oscillator may comprise comprises an oscillator core configured for contributing gain to oscillations generated in the oscillator and a frequency tuning network connected between the oscillator core and a signal source that provides an input signal for creating the oscillations in the oscillator. The frequency tuning network may be configured for tuning frequency of the oscillations, to inhibit amplifying a first capacitance from the oscillator core and to amplify a second capacitance from the frequency tuning network. The frequency of oscillations may be tuned by varying a capacitance, and isolating one or more of noise sources or parasitic capacitances from the tuning network.

Voltage-controlled oscillator and a method for tuning oscillations

A voltage-controlled oscillator and a method for tuning oscillations. The oscillator comprises a resonator input connected to an oscillator core and a frequency tuning network. The oscillator core and resonator input are isolated from the frequency tuning network by inductors. The method comprises generating oscillations, tuning the frequency of the oscillations by varying a capacitance, and isolating one or more of noise sources or parasitic capacitances from the tuning network.

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Bengaluru, India

Bharath Kumar Singareddy