Intel Corporation

Netapp, Inc.

Bharath Kumar

Naveen G

Robert E Gough

Sameer Kp

Mallari C Hanchate

Naveen Gopal Reddy

Nandhini Venkataraman

Ganesh R St

Raymond Sinnappan

Two extended embedded Display Port displays may be enabled by using a single set of panel power sequencing (PPS) signals from a chipset to enable the two embedded Display Port panels. To enhance the user experience, the backlight module brightness is controlled by making use of a pin available on a system on a chip (SOC) and modification of drivers. This helps to save power when only one panel is used. When both panels are used simultaneously, power savings can be achieved by using backlight control signals.

Enabling a chipset that supports a single display to support dual display

Technology for a system operable to extend a level of processor performance is disclosed. The system can comprise a power source connected to a platform voltage regulator (VR) and one or more processors and configured to provide an input power to the platform VR. The system can further comprise the platform VR connected to a peripheral interface and the one or more processors and configured to power the peripheral interface and send a power good signal to the one or more processors. The system can further comprise the peripheral interface connected to the platform VR and the one or more processors and configured to connect to a peripheral device and send a signal to the one or more processors when a peripheral interface connection state is identified as connected.

Extending processor performance

A method, non-transitory computer readable medium and computing device that determines in response to an event when currently owned spare data storage devices by one of a pair of storage node computing devices in a high availability pair are insufficient to satisfy a requirement for the event for one or more additional spare data storage devices having one or more data storage device parameters. One or more currently owned spare data storage devices by the other one of the storage node computing devices sufficient to satisfy the requirement are identified. The identified one or more currently owned spare data storage devices owned by the other one of the pair of storage node computing devices that satisfy the requirement are assigned to the one of the pair of storage node computing devices.

Methods for providing global spare data storage device management and devices thereof

Methods and apparatus relating to reducing pin count requirements for implementation of interconnect idle state(s) are described. In one embodiment, logic receives a general purpose input signal on a signal pin of an Input/Output (I/O) complex logic in response to a control signal. An I/O device (e.g., coupled to the I/O complex logic) enters a low power consumption state in response to the control signal. The logic receives a wake signal on the signal pin of the I/O complex logic and the I/O device exits the low power consumption state in response to the wake signal. Other embodiments are also claimed and disclosed.

Growing community of inventors

Bengaluru, India

Bharath Kumar