International Business Machines Corporation

Bharat Sukhwani

Sameh W Asaad

Mathew S Thoennes

Hong Min

Parijat Dube

Balakrishna Raghavendra Iyer

Robert J Halstead

Donald W Schmidt

Mohit Kapur

Bernard V Brezzo

Donna N Eng Dillenberger

Gong Su

Roger Moussalli

Matthew S Thoennes

Sameh W Assad

A computer-implemented method, system and computer program product for minimizing hash collisions of composite keys. Each component ('key component') of the composite key is converted into a linear index that uniquely represents that key component. Such a one-to-one mapping reduces the length (i.e., range of values the key component represents) of each component without introducing any collisions thereby effectively resulting in the lossless compression of the individual key components. Such a linear index for each converted key component is stored in a separate lookup memory. A reduced composite key is then created by joining together the linear indices that represent the components of the composite key thereby reducing the total length or domain (i.e., range of values the composite key represents) of the original composite key in a lossless manner. In this manner, by reducing the total length of the composite key, hash collisions of composite keys are minimized.

Minimizing hash collisions of composite keys

Managing hardware function requests incurring variable response latencies is provided. A request for a hardware function is received from a requesting program. The requested hardware function is expected to incur a variable response latency and is implemented as a main hardware function and a retry hardware function. The main hardware function is executed. It is determined whether a fixed response latency of the main hardware function has been exceeded. A response is returned with a retry flag to the requesting program. The retry flag directs the requesting program to issue a request for the retry hardware function after an interval of time. A unique identifier corresponding to the main hardware function is provided to the requesting program.

Non-blocking hardware function request retries to address response latency variabilities

Techniques are provided for data filtering using hardware accelerators. An apparatus comprises a processor, a memory and a plurality of hardware accelerators. The processor is configured to stream data from the memory to a first one of the hardware accelerators and to receive filtered data from a second one of the hardware accelerators. The plurality of hardware accelerators are configured to filter the streamed data utilizing at least one bit vector partitioned across the plurality of hardware accelerators. The hardware accelerators may be field-programmable gate arrays.

Data filtering using a plurality of hardware accelerators

Embodiments include methods, systems and computer program products for performing a tournament tree sort on a hardware accelerator having an external memory. The method includes receiving a plurality of key values by the hardware accelerator, assigning each of the plurality of key values a sequential key number as the plurality of key values are received and performing pairwise comparisons of each of the plurality of key values to identify a winning key and a losing key. The method also includes storing the losing key of each pairwise comparison in a first section of the external memory, wherein a location in the first section is based on the key number of the losing key and storing the winning key of each pairwise comparison in a second section of the external memory, wherein a location in the second section is based on the key number of the winning key.

Hardware implementation of a tournament tree sort algorithm using an external memory

Embodiments include methods, systems and computer program products for offloading multiple processing operations to an accelerator. Aspects include receiving a database query from an application, performing an analysis on the query, and identifying a plurality of available accelerators. Aspects further include retrieving cost information for one or more templates available on each of the plurality of available accelerators, determining a query execution plan based on the cost information and the analysis on the query, and offloading one or more query operations to at least one of the plurality of accelerators based on the query execution plan.

Scalable acceleration of database query operations

Embodiments include methods, systems and computer program products a for offloading multiple processing operations to an accelerator includes receiving, by a processing device, a database query from an application. The method also includes performing analysis on the database query and selecting an accelerator template from a plurality of accelerator templates based on the analysis of the database query. The method further includes transmitting an indication of the accelerator template to the accelerator and executing at least a portion of the database query on the accelerator.

Accelerating multiple query processing operations

Methods and arrangements for mapping a query operation to an accelerator are provided. The method includes receiving, by a processor, a query operation and determining the design logic of the query operation, receiving a configuration of one or more available accelerators and a design logic of each of the one or more available accelerators, and determining if the query operation can be offloaded to one or more of the one or more available accelerators. Based on a determination that the query operation can be offloaded to one or more of the one or more available accelerators, the method also includes creating software structures to interface with a selected accelerator and executing the query operation on the selected accelerator. Based on a determination that the query operation cannot be offloaded to one or more of the one or more available accelerators, the method further includes executing the query operation in software.

Mapping query operations in database systems to hardware based query accelerators

A computer-implemented method includes determining that a database query warrants a first projection operation to project a plurality of input rows to a plurality of projected rows, where each of the plurality of input rows has one or more variable-length columns. A first projection control block is constructed, by a computer processor, to describe the first projection operation. The first projection operation is offloaded to a hardware accelerator. The first projection control block is provided to the hardware accelerator, and the first projection control block enables the hardware accelerator to perform the first projection operation at streaming rate.

Offloading projection of fixed and variable length database columns

Embodiments include methods, systems and computer program products for performing a composite sort on a tunable hardware sort engine includes determining desired sort performance parameters, configuring a composite sort engine based on the desired sort performance parameters, and receiving a plurality of keys having a payload associated with each of the plurality of keys. The method also includes reserving DRAM storage for each of the payloads, generating a tag for each of the plurality of keys, the tag identifying the DRAM storage reserved for each of the payloads, and storing the payloads in the portions of the DRAM storage. The method further includes generating a composite key for each of the plurality of keys, sorting the composite keys by the composite sort engine, and retrieving the payloads associated with the sorted composite keys from the DRAM storage. The method also includes outputting the payloads associated the sorted composite keys.

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Briarcliff Manor, NY, United States of America

Bharat Sukhwani