Intel Corporation

Microsoft Technology Licensing, LLC

Bharat S Pillilli

Mojtaba Bisheh Niasar

Eswaramoorthi Nallusamy

Nikola Radovanovic

David W Palmer

Reshma Lal

Bryan David Kelly

Johan G Van De Groenendaal

Vishal Soni

Emre Karabulut

Saravana Priya Ramanathan

Mahesh S Natu

Vivek Garg

Ishwar Agarwal

Ramamurthy Krithivas

Venkatesh Ramamurthy

Purushottam Goel

Michael Berger

Phani Kumar Kandula

Xiaoyu Ruan

Peter J Smith

Suresh Chemudupati

Yi-Feng Liu

Harikrishna B Baliga

Shlomi Alkalay

Johan Van De Groenendaal

Michael S Yu

Montgomery multiplier architectures are provided. A circuit can include an initial processing element (PE) circuit configured to generate a first output including (i) a radix of a carry out and (ii) a radix of an intermediate result based on radixes of respective operands, a radix of an inverse of a modulus, and a radix of the modulus, middle PE circuits configured to generate a second output including (i) respective radixes of a Montgomery multiplication result and (ii) further respective radixes of a carry out on two consecutive clock cycles based on the first output, and a final PE circuit configured to generate further radixes of the Montgomery multiplication results on two consecutive, subsequent clock cycles based on the second output.

Montgomery multiplier architecture

Test inputs are iteratively provided to a target asymmetric cryptographic system. Trace information resulting from operation of the cryptographic system is received corresponding to processing each test input. For each test input, test vector leakage assessment (TVLA) is performed on the trace information for the test input, t-values are stored, and the trace information is erased before proceeding to a next test input. In one example, a mean and variance of the trace information is updated for each test input.

Cryptographic system real-time test vector leakage assessment

A hash-based cryptographic system includes hash input registers and hash generators coupled in parallel with each other. Each hash generator of the hash generators is coupled to receive a corresponding hash input from one of the input registers. A controller is coupled to the input registers and configured to provide the corresponding hash input to the hash registers to cause the parallel hash generators to generate a private key for corresponding leaf nodes of a hash-based signature tree structure.

Hash based cryptography accelerator

Masked scalar blinding circuits for a side channel analysis (SCA) attack countermeasure are provided. A circuit can include logic gates configured to receive a private key and generate a first private key value and a second private key value that sum to the private key, a first multiplier configured to generate a first product based on a first random number and a multiplicative group order, a second multiplier configured to generate a second product based on a second random number and the multiplicative order group, and circuitry configured to generate a result and a carry out, based on the first private key value, second private key value, the first product, and the second product.

Elliptic curve cryptography masked blinding countermeasure

A computer implemented method includes receiving data on which to perform elliptic curve digital signature algorithm (ECDSA) and mapping ECDSA computations from affine coordinates to projective coordinates. A complete addition formula is executed on the data with operations changing based on bits of a secret key by minimizing execution time and power consumption differences via a finite adder. Modular multiplications are executed via a finite multiplier module. At least one countermeasure selected from the group consisting of randomizing a base point, generating a secret key using a two random number seed random number generator, using a randomized secret key to generate a signature, and randomizing signature generation is executed.

Side channel attack resistant cryptographic accelerator

A computer platform is disclosed. The computer platform comprises a central processing unit (CPU) including at least one socket having a plurality of tiles and control circuitry to partition the socket into a plurality of sub-sockets and assign a unique identity to each of the plurality of sub-sockets for security verification, wherein each sub-socket comprises at least one of the plurality of tiles to operate as a cluster of resources.

Partitioned platform security mechanism

Generally discussed herein are devices, systems, and methods for digital signature generation security. A method can include generating, by a first device, a first random number, in generating a signature for a communication, masking, using the first random number, only a private key, a hash of the communication, or a combination thereof, and providing the signature with the communication to a second device.

Low-cost, high-security solutions for digital signature algorithm

Generally discussed herein are devices, systems, and methods for secure cryptographic masking. A method can include generating a first random number, determining a result of the first random number modulo a prime number resulting in a second random number, subtracting the second random number from the prime number resulting in a first subtraction result, adding a private key value to the first subtraction result resulting in a first split, and responsive to determining the private key value is less than the random number, providing the first split and the second random number as splits of the private key.

Simplified masking for signed cryptography operations

Systems and methods related to flush plus reload cache side-channel attack mitigation are described. An example method for mitigating a side-channel timing attack in a system including a processor having at least one cache is described. The method includes receiving a first instruction, where the first instruction, when executed by the processor, is configured to flush at least one cache line from the at least one cache associated with the processor. The method further includes, prior to execution of the first instruction by the processor, automatically mapping the first instruction to a second instruction such that the at least one cache line is not flushed from the at least one cache even in response to receiving the first instruction.

Systems and methods for flush plus reload cache side-channel attack mitigation

Techniques for ensuring address translation services (ATS) functionality is used correctly and safely for any type of device that supports ATS, even for devices that might potentially be acting in a rogue manner, are disclosed. A host performs an integrity check on a device that uses ATS to prevent the device from maliciously using a locally cached HPA. The device submits a first ATS-enabled request to the host. The device receives metadata comprising (i) a first integrity check vector (ICV) that is usable to authenticate the device, (ii) the HPA, and (iii) an initialization vector (IV). The device locally caches the metadata in an address translation cache (ATC). The device submits a second ATS-enabled request, which includes the metadata. The host then independently authenticates the device using the received metadata in the request.

Securing ATS from rogue devices for confidential computing

Apparatus and methods for booting and using a single CPU socket as a multi-CPU partitioned platform. The single CPU socket includes a plurality of core tiles that a partitioned into a plurality of virtual clusters comprising CPU sub-sockets. Each of the CPU sub-sockets in coupled to an Input-Output (IO) tile having an integrated boot support block and comprising a plurality of IO interfaces including at least one IO interface configured to receive boot signals for booting the sub-sockets and an IO interface to access boot firmware stored in a firmware storage device coupled to the IO interface. The integrated boot support block is configured to facilitate booting of each of the plurality of CPU sub-sockets using a shared set of boot resources coupled to the plurality of IO interfaces.

Booting and using a single CPU socket as a multi-CPU partitioned platform

Techniques are described herein that are capable of reducing latency of changing an operating state of a processor from a low-power state to a normal-power state. For example, providing a notification from a hardware system to the processor or receiving the notification at the processor, indicating that a transaction layer packet will be provided to the processor at a future time, may trigger the processor to change the operating state from the low-power state to the normal-power state. In another example, receipt of a transaction layer packet at the processor from a hardware system may trigger the processor to change the operating state from the low-power state to the normal-power state.

Reducing latency of changing an operating state of a processor from a low-power state to a normal-power state

Examples described herein a firmware update device to execute a second firmware, in place of execution of a first firmware, in response to an instruction that causes the firmware update device to execute the second firmware, wherein the second firmware is copied to a buffer prior to execution of the instruction. In some examples, one or more processors are to execute the instruction that causes the firmware update device to execute the second firmware. In some examples, prior to execution of the instruction, a device root of trust is also to validate the second firmware.

Firmware update technologies

A system for granular reset management without reboot is disclosed. The system may include a subsystem, a processor including a reset management circuit coupled to the subsystem. The reset management circuit may include circuitry to receive a command to reset the subsystem, determine whether the subsystem can be reset without performing a system wide reboot, and based on a determination that the subsystem can be reset without performing a system wide reboot, block the use of the subsystem, drain the subsystem, and reset the subsystem. Circuity and method are also disclosed.

Growing community of inventors

El Dorado Hills, CA, United States of America

Bharat S Pillilli