Intel Corporation

Bharat N Zaveri

Michael J Morrison

Nazar A Zaidi

Frederick R Gruner

Syed A Zaidi

Nimish H Modi

Andrew Paul Kelm

The invention provides a system and method which can be used for pre-decoding one-byte instruction prefixes and branch instruction indicators. A static line detect generates a number of instruction indicators. Further, a prefix and branch decode unit combines at least two of the number of instruction indicators, and a pre-decode unit decodes the combined instruction indicators. Embodiments of the invention decode one byte prefixes without additional cycle penalty and generate one and two byte branch indications early.

Length decode to detect one-byte prefixes and branch

A microprocessor includes a decoder, a queue, and a renamer. The decoder is adapted to receive a program instruction and decode the program instruction to provide a first decoded instruction. The first decoded instruction includes a plurality of instruction bits. The queue is coupled to the decoder and adapted to store the first decoded instruction. The renamer has a first input port and a first and second output port. The renamer is coupled to the queue and adapted to receive the first decoded instruction at the input port, provide the first decoded instruction on the first output port, change at least one of the instruction bits to generate a second decoded instruction, and provide the second decoded instruction on the second output port. A method for expanding program instructions in a microprocessor having a renamer is provided. The renamer includes a first input port and first and second output ports. The method includes receiving a first decoded instruction in the first input port. The first decoded instruction includes a plurality of instruction bits. At least one of the instruction bits of the first instruction is changed to generate a second instruction. The first decoded instruction is provided on the first output port, and the second decoded instruction is provided on the second output port.

Method and apparatus for expanding instructions

A queue structure includes a plurality of entries, a plurality of ports coupled to the entries, a plurality of enable lines coupled to the entries and the ports, and control logic. Each enable line is adapted to enable a selected port to communicate with a selected entry. The control logic is adapted to enable at least two enable lines and allow at least one of the ports to communicate with at least two of the entries concurrently. A method for storing data in a queue is provided. The queue includes a plurality of entries, a plurality of ports coupled to the entries, and a plurality of enable lines coupled to the entries and the ports. Each enable line is adapted to enable a selected port to communicate with a selected entry. The method includes receiving a first instruction on one of the ports. A first enable line is enabled to allow the port to communicate with a first entry. The first instruction is stored in the first entry. A second enable line is enabled concurrent with enabling the first enable line to allow the port to communicate with a second entry. The first instruction is stored in the second entry.

Method and apparatus for queuing data

A microarchitecture that accommodates divergent instruction sets having different data sizes and addressing modes utilizes a mechanism for translating a generic flow for an instruction into specific operations at run-time. These generic flows use a special class of micro-ops (uops), called 'super-uops' (or 'Suops)' which are translated into a variable number of regular (i.e., simple) uops. A first-level decoder translates macroinstructions into either simple micro-ops or one or more super-uops which represent one or more sequences of one or more simple uops. A second-level decoder is responsible for converting the super-uops into the appropriate micro-op sequence based upon a set of arguments associated with the super-uop and attributes of the macroinstruction.

Computer utilizing special micro-operations for encoding of multiple

Apparatus for increasing the decoding speed of a microprocessor. The apparatus includes a first decoder for decoding macroinstructions. The first decoder includes apparatus for generating a single initial microinstruction vector from simple macroinstructions and from complex macroinstructions having a beginning microinstruction equivalent to a microinstruction for a simple macroinstruction. The first decoder also includes apparatus for indicating a beginning address for generating any remaining microinstruction vectors for a complex macroinstruction decoded by the first decoder. The apparatus for increasing the decoding speed of a microprocessor also includes apparatus, coupled to the first decoder, for generating any remaining microinstruction vectors for complex macroinstructions decoded by the first decoder. The apparatus for generating any remaining microinstruction vectors includes apparatus for responding to the apparatus for indicating a beginning address.

Growing community of inventors

San Jose, CA, United States of America

Bharat N Zaveri