Intel Corporation

Bharat M Pathak

Aliasgar S Madraswala

Sanjay S Talreja

Mase J Taub

Mickey L Fandrich

Rodney R Rozman

Naveen Prabhu Vittal Prabhu

Binh N Ngo

Violante Moschiano

Pranav Kalavade

Rajesh Sundaram

Michele Incarnati

Yogesh B Wakchaure

Walter Di Francesco

Raymond W Zeng

Owen W Jungroth

Robert E Larsen

Kristopher H Gaewsky

Christopher John Haid

Vishram P Dalvi

Karthikeyan Ramamurthi

Edward M Babb

Antonino Giuseppe La Spina

Rupinder K Bains

Marcus E Landgraf

A memory device that has been programmed to store a single bit or multiple bits can perform a determination of a number of threshold voltages in one or more threshold voltage level regions. Based on the number of threshold voltages meeting or exceeding a threshold level, a page of bits can be read and if the bit error rate of the page of bits is below a threshold rate, the page of bits can be stored in the cells together with other bits stored in the cells and a provided additional page of bits. However, if the bit error rate of the page of bits is at or above the threshold rate, then the bit or bits stored in the cells can be error corrected and stored together with a provided additional page of bits.

Memory programming techniques

A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.

System and method for performing a concurrent multiple page read of a memory array

In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory device comprising a plurality of NAND flash memory units. The storage device is to determine that the NAND flash memory device did not pass an initialization procedure; identify a first addressing scheme that is implemented by one or more of the NAND flash memory units that initialized properly; and after the initialization procedure, instruct each of the plurality of NAND flash memory units to implement the first addressing scheme.

Method and apparatus for avoiding bus contention after initialization failure

A circuit includes (i) an N-channel device having a gate, a source connected to low voltage, and a drain connected to a memory select gate, (ii) a P-channel device having a gate, a source, and a drain connected to the drain of the N-channel device, and (iii) a voltage supply connected to the source of the P-channel device, the voltage supply switching between a first high voltage and a first lower voltage. A gate driver supplies, to the gates of the N-channel and P-channel devices, a second high voltage, a second low voltage, or an intermediary voltage between the second high voltage and second low voltage. The gate driver supplies the intermediary voltage when the voltage supply switches between the first high voltage and first lower voltage.

Voltage driver for a memory

An operation control method and apparatus are described. The apparatus includes a timer circuit, a blocking circuit and a control circuit. The timer circuit provides a done signal upon completion of timing a predetermined elapsed time interval initiated by a start signal. The blocking circuit receives the done signal and provides the done signal as output if the done signal is not blocked when received. The control circuit receives a begin signal indicating that the operation is to be performed and a limit signal to indicate whether or not a condition exists that would prevent the operation from being completed in a single step. If the limit signal indicates the operation can be completed in the single step, the control circuit starts the timing circuit and controls performance of the single step until the done signal is received. If the limit signal indicates the operation cannot be completed in the single step, the control circuit divides the single step into at least two sub-steps, during each sub-step, the control circuit starts the timing circuit and controls performance of the sub-step until the done signal is received. The control circuit blocks output of the done signal from the blocking circuit during each sub-step until a final sub-step. For one embodiment, the operation to be performed is an erase operation specified by a write state machine that specifies an erase block to be erased within a flash memory. Alternately, the operation to be performed is a program operation specified by a write state machine that specifies data to be programmed within a flash memory.

Controlling flash memory program and erase pulses

A power supply lockout circuit that prevents corruption of nonvolatile writeable memory data is described. The power supply lockout circuit monitors the power supply signals from several power supplies. The power supply lockout circuit locks out commands writing to the nonvolatile writeable memory when any one of the monitored power supply signals coupled to the nonvolatile writeable memory is below a specified signal level. The power supply lockout circuit includes a detector which provides a lockout signal to the nonvolatile writeable memory when a power supply signal is less than a prespecified voltage. The power supply lockout circuit also includes a sampling circuit which provides other lockout signals to the nonvolatile writeable memory when a different power supply signal is less than a reference voltage.

Input/output power supply detection scheme for flash memory

Growing community of inventors

Folsom, CA, United States of America

Bharat M Pathak