Qualcomm Incorporated

Bharat Kumar Rangarajan

Rajesh Arimilli

Srinivas Turaga

Rakesh Misra

Keith Alan Bowman

Dipti Ranjan Pal

Vijayakumar Ashok Dibbad

Raghavendra Srinivas

Chulmin Jung

Matthew Levi Severson

Gordon P Lee

Shih-Hsin Jason Hu

Prashanth Kumar Kakkireni

Chandan Agarwalla

Varun Jindal

Rengarajan Ragavan

Ateesh Deepankar De

Aspects of the disclosure are directed to a quality of service (QOS) assignment policy for processor applications in a system on a chip (SoC). In accordance with one aspect, the system on a chip (SoC) includes an applications central processing unit (CPU), wherein the applications CPU comprises a quality of service (QOS) database table configured to list a plurality of QoS metrics associated with a plurality of processor threads, wherein at least one of the plurality of QoS metrics is used to determine a dynamic clock and voltage scaling (DCVS) operating point; a graphics processing unit (GPU) coupled to the applications CPU; and a common interconnection databus coupled to the applications CPU and the GPU.

Quality of service (QoS) control of processor applications

A method to prevent a malicious attack on CPU subsystem (CPUSS) hardware is described. The method includes auto-calibrating tunable delay elements of a dynamic variation monitor (DVM) using an auto-calibration value computed in response to each detected change of a clock frequency (Fclk)/supply voltage (Vdd) of the CPUSS hardware. The method also includes comparing the auto-calibration value with a threshold reference calibration value to determine whether the malicious attack is detected. The method further includes forcing a safe clock frequency (Fclk)/safe supply voltage (Vdd) to the CPUSS hardware when the malicious attack is detected.

On-die voltage-frequency security monitor

Task scheduling in a computing device may be based in part on voltage regulator efficiency. For an additional task to be scheduled, multiple task scheduling cases may be determined that represent execution of the additional task on each of a number of processors concurrently with one or more other tasks executing among the processors. For each task scheduling case, a regulator input power level for a voltage regulator may be determined based on a performance level indication associated with the additional task, the one or more other tasks executing on the processors, and the efficiency level of each voltage regulator. For each task scheduling case, a total regulator input power level may be determined by summing the regulator input power levels for all voltage regulators. The additional task may be executed on a processor associated with a task scheduling case for which total regulator input power is lowest.

Core voltage regulator energy-aware task scheduling

Various embodiments include methods and devices for system on chip infrastructure of system on chip infrastructure secure memory access and power management. Some embodiments, include determining whether a processor is performing a secure memory access transaction, and gating a clock signal from being transmitted to a secure portion of a memory in response to determining that the processor is not performing a secure memory access transaction. Some embodiments include determining whether any processor is operating in a secure mode, and transmitting a retention signal to the secure portion of the memory in response to determining that no processor is operating in a secure mode. The retention signal may be configured to set a retention state for the secure portion of the memory.

Processor security mode based memory operation management

In certain aspects, a tag memory comprises a plurality of non-configurable tag columns configured to be powered on during a normal operation; and a plurality of configurable tag columns, wherein a first portion of the plurality of configurable tag columns is configured to be powered off during the normal operation and a second portion of the plurality of configurable tag columns is configured to be powered on during the normal operation.

System physical address size aware cache memory

Various embodiments include methods and devices for cache memory power control. Some embodiments may include determining whether a processor is entering a lowest power mode of the processor, and switching a lowest power mode switch control signal to indicate to a cache power switch of the processor switching an electrical connection of a cache memory from a memory power rail to a processor power rail in response to determining that the processor is entering a lowest power mode.

Method and system for improving rock bottom sleep current of processor memories

In controlling power in a portable computing device ('PCD'), a power supply input to a PCD subsystem may be modulated with a modulation signal when an over-current condition is detected. Detection of the modulation signal may indicate to a processing core of the subsystem to reduce its processing load. Compensation for the modulation signal in the power supply input may be applied so that the processing core is essentially unaffected by the modulation signal.

Power controller communication latency mitigation

Various aspects are described herein. In some aspects, the disclosure provides selective coupling of portions of a memory structure to voltage supplies. Certain aspects provide a computing device. The computing device includes a memory comprising a plurality of portions that are individually power collapsible. The computing device further includes a first voltage rail supplying a first voltage. The computing device further includes a second voltage rail supplying a second voltage. The computing device further includes a plurality of switching circuits, each switching circuit configured to selectively couple a corresponding one of the plurality of portions with the first voltage rail or the second voltage rail. The computing device further includes a controller configured to control each of the plurality of switching circuits based on a current active mode of the memory, and a current operating mode of each of the plurality of portions.

Selective coupling of memory to voltage rails for different operating modes

Various aspects are described herein. In some aspects, the disclosure provides techniques for accessing tag information in a memory line. The techniques include determining an operation to perform on at least one memory line of a memory. The techniques further include performing the operation by accessing only a portion of the at least one memory line, wherein the only the portion of the at least one memory line comprises one or more flag bits that are independently accessible from remaining bits of the at least one memory line.

Asymmetric memory tag access and design

Selective coupling of memory to voltage rails based on operating mode of processor

Method and Apparatus for automatically switching to a low power retention mode based on architectural clock gating is disclosed. In some implementations, a system includes a central processing unit (CPU), comprising a clock gating cell configured to receive a clock enable signal. The system further includes a switching module configured to monitor the clock enable signal and to cause a power manager to switch the CPU from a first power supply output to a second power supply output in response to the clock enable signal changing from a first state to a second state.

Method and apparatus for automatic switch to retention mode based on architectural clock gating

Systems, methods, and apparatus for operating a central processing unit (CPU) are provided. The CPU includes a plurality of memories including a first group of memories and a second group of memories. The plurality of memories are grouped based on a timing criticality of each memory. The CPU further includes a memory core (MX) voltage supply configured to provide the plurality of memories with an MX voltage, an application processor core (APC) voltage supply configured to provide the plurality of memories with an APC voltage, and a voltage switching circuit. The voltage switching circuit detects an operating mode of the CPU and switches a voltage provided to at least one of the first group of memories or the second group of memories between the MX voltage and the APC voltage based on a type of the operating mode detected.

Grouping central processing unit memories based on dynamic clock and voltage scaling timing to improve dynamic/leakage power using array power multiplexers

In some aspects, a method for managing leakage power includes coupling a first supply rail to a cache memory if a processor is in a first performance mode, wherein the processor accesses the cache memory, and coupling a second supply rail to the cache memory if the processor is in a second performance mode. The method also includes detecting gating of a clock signal to the cache memory or the processor, and, upon detecting gating of the clock signal, switching the cache memory from the second supply rail to the first supply rail if the cache memory is currently coupled to the second supply rail.

Growing community of inventors

Bengaluru, India

Bharat Kumar Rangarajan