Qualcomm Incorporated

Bharat Kavala

Abinash Roy

Raghavendra Srinivas

Bapana Naidu Pudi

Abhijit Joshi

Certain aspects of the present disclosure generally relate to optimizing, or at least reducing, power consumption and/or hold timing issues within an integrated circuit (IC). One example IC generally includes a global power supply rail and a first power block. The first power block includes a first plurality of head switch cells coupled to the global power supply rail. Each head switch cell includes a head switch coupled between the global power supply rail and a power node for the head switch cell. The first plurality of head switch cells is configured such that a first set of the first plurality of head switch cells can be programmed on and a second set of the first plurality of head switch cells can be programmed off.

Local configuration using programmable header switch

Various aspects are described herein. In some aspects, the disclosure provides techniques for reducing latency in switching computing cores of a computing system between operating modes. Certain aspects provide a computing device including a plurality of computing cores, each configured to operate in any one of a plurality of operating modes. The computing device further includes a first voltage rail and a plurality of components, each associated with one of the computing cores. The computing device further includes a plurality of switches, each switch configured to selectively couple a corresponding one of the plurality of components to the first voltage rail. The computing device further includes a controller configured to determine a current operating mode of each of the plurality of computing cores and switch the plurality of switches at a first selected switching rate based on the determined current operating mode of each of the plurality of computing cores.

Growing community of inventors

Visakhapatnam, India

Bharat Kavala