Hewlett-packard Company

Hewlett-packard Development Company, L.p.

Bharat K Singh

Bruce W Melvin

Patricia Ann Thaler

Bruce Anthony Klemin

Ronald McBride

Kittur Nagesh

Michael Richard James

David Kuntz

The present invention provides an improved shared memory switching method in which a guaranteed minimum number of buffers per output port is reserved for each input port. The shared memory may also be optionally divided into reserved and unreserved buffers, with the guaranteed minimum number of buffers being provided from the reserved buffers. The unreserved buffers are available to any port and will handle burst communications and other events that cause a given input port's allocation of reserved buffers to be exhausted. So that bursts are also handled fairly among input ports, additional optional features of the present invention include limiting the number of unreserved buffers that may be consumed by a single input port. For fairness among output ports, method also preferably fairly allocates unreserved buffers among the output ports.

Nonblocking and fair queuing switching method and shared memory packet switch

A first device detects whether a second device implements full duplex communication. When the first device begins receiving a network packet from the second device, the first device transmits a jam signal to the second device. When transmission of the network packet from the second device to the first device has been completed, the first device determines whether a check value within the network packet is valid. When the check value is valid, the first device recognizes that the second device implements full duplex communication. When the check value is not valid, the first device recognizes that the second device does not implement full duplex communication.

Automatic detection of full or half duplex capability in a remote network device

A dual channel 100Base-T link for use between devices in a computer network system. The IEEE 802.3 standard for bus network systems calls for a device interconnection cable which includes four twisted pairs of wire. For 10BaseT and 100Base-T systems, the 802.3 standard specifies the use of only two of the four pairs. The present link includes a special Media Access Controller having dual channel interconnections, and primary and secondary Media Independent Interfaces and Physical Layers. This provides first and second communication channels which are parallel, but cooperating. The second channel is connected to the normally unused two pairs in the cable, effectively doubling the bandwidth of the link without running a new cable.

Dual channel 100Base-T link for computer networks

A configuration apparatus for network devices. A plurality of LEDS on the front panel of a network device has a primary mode, displaying device and port status. These LEDS are grouped in a matrix, consisting of pairs of LEDS arranged in a plurality of parallel columns. Textual information may be provided adjacent each of the pairs, to describe an associated secondary mode, for configuration of the features and operational states of the device. When a configuration switch and mode control circuitry are enabled, drivers for the LEDS are disconnected from the ports. A configuration cycle is initiated, during which at least some of the LEDS provide visual cues to the user for carrying out the configuration operations. Sequential and unison blinking of the LEDS, as a group, individually, and in pairs, confirms reconfiguration opportunity, selection, and execution, for each secondary function.

Apparatus and method for configuring a computer networking device

A processor performs data transactions. For a first data transfer between the processor and a first external device which uses non-multiplexed data transactions, a first address is placed on an (external) address bus and first data is transferred on an (external) address/data bus. A second data transaction is performed between the processor and a second external device which uses multiplexed data transactions. In an address phase of the second data transaction, a second address is placed on the address/data bus. In a data phase of the second transaction, second data is transferred on the address/data bus.

Microprocessor with versatile addressing

A loopback connector system for testing token ring components such as routers or interface assemblies with requiring that the component to be tested be connected into the local area network (LAN). The connector permits the component to be tested to be isolated from the LAN, permitting the integrity of the component to be tested without regard to the integrity of lobe cables or other devices on the ring, and without degrading network performance. The connector system includes two different multi-pin connector types, a DB9 and an RJ45 connector, used to connect into the network, separated by a short two-pair cable. Resistors used to simulate the network loading on the component are connected between appropriate pins, with the resistors being shared between the two types of connectors.

Growing community of inventors

Roseville, CA, United States of America

Bharat K Singh