Oracle America, Inc.

Sun Microsystems, Inc.

Oracle International Corporation

Bharat K Daga

Robert Cypher

Thomas M Wicki

Jurgen M Schulz

Haakan E Zeffer

Brian McGee

Some embodiments of the present invention provide a system that maps an address to an entity, wherein the mapping interleaves addresses between a number of entities. During operation, the system receives an address A from a set of X consecutive addresses, wherein the address A is to be mapped to an entity E in a set of Y entities, and wherein Y need not be a power of two. Next, the system obtains F=floor(log(Y)) and C=ceiling(log(Y)). The system then calculates L, which equals the value of the F least-significant bits of A. The system also calculates M, which equals the value of the C most-significant bits of A. Next, the system calculates S=L+M. Finally, if S&#x3c;Y, the system sets E=S. Otherwise, if S&#x2267;Y, the system sets E=S&#x2212;Y.

Efficient interleaving between a non-power-of-two number of entities

A memory system that facilitates probabilistic error correction for a failed memory component with partial-component sparing. The memory system accesses blocks of data, each block including an array of bits logically organized into R rows and C columns. The C columns include () a row-checkbit column containing row-parity bits for each of the R rows, () an inner-checkbit column containing X=R&#x2212;S inner checkbits and S spare bits, and () C-2 data-bit columns containing data bits. Each column is stored in a different memory component. When the memory system determines that a memory component has failed, the memory system examines the pattern of errors associated with the failed component to determine if the failure affects a partial component associated with S or fewer bits. If so, the memory system corrects and remaps data bits from the failed partial component to the S spare data bits in the inner-checkbit column.

Memory system that supports probalistic component-failure correction with partial-component sparing

Some embodiments of the present invention provide a system that processes a request for a cache line in a multiprocessor system that supports a directory-based cache-coherence scheme. During operation, the system receives the request for the cache line from a requesting node at a home node, wherein the home node maintains directory information for all or a subset of the address space which includes the cache line. Next, the system performs an action at the home node, which causes a valid copy of the cache line to be sent to the requesting node. The system then completes processing of the request at the home node without waiting for an acknowledgment indicating that the requesting node received the valid copy of the cache line.

Bandwidth-efficient directory-based coherence protocol

A memory system accesses a block of data, each block including bits logically divided into rows and columns, each column including a row-checkbit column, an inner-checkbit column, and data-bit columns. Each column is stored in a different memory component, and checkbits are generated from databits to provide block-level correction for a failed memory component, and double-error correction for errors in different memory components. The system calculates a row syndrome and an inner syndrome for the block of data, the inner syndrome resulting from any two-bit error in the same row being unique. The system can use the row and inner syndromes to determine whether errors are associated with a failed memory component. If not, the system can use the row and inner syndromes, and inner syndromes for all possible combinations of one-bit errors occurring in two rows with a row syndrome of one to correct two bits.

Memory system that provides guaranteed component-failure correction with double-error correction

Some embodiments of the present invention provide a system that can be reconfigured to provide error detection and correction after a failure of a memory component in a memory system. During operation, the system accesses a block of data from the memory system, wherein each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including two checkbit columns containing checkbits, and C&#x2212;2 data-bit columns containing data bits, wherein each column is stored in a different memory component, and wherein the checkbits are generated from the data bits to provide block-level detection and correction for a failed memory component. Next, upon examining the block of data, the system determines that a specific memory component in the memory system has failed. If the failed memory component contains a data-bit column for the block of data, the system uses checkbits from the two checkbit columns to correct the data-bit column, and then stores the corrected data-bit column. Next, the system generates and stores new checkbits in a functioning memory component, wherein the new checkbits provide single-error-correction and double-error-detection for erroneous bits in the block of data, but do not provide for detection and correction of a failed memory component.

Facilitating error detection and correction after a memory component failure

A multiple clock domain system. A system comprises two clock domains which receive a source clock signal. The first domain includes a first clock signal with a first frequency and the second domain includes a second clock signal with a second frequency. A ratio of the first frequency to the second frequency is N:M. The first domain is configured to initialize a count to N, if N is less than 2*M; and initialize the count to M, if N is not less than 2*M. Subsequently, on each cycle of the first clock signal, the first domain adds (M-N) to the count and asserts a sample enable signal, if the count is greater than or equal to N; and adds a value equal to M to the count and negates the sample enable signal, if the count is not greater than or equal to N.

Generating a clock crossing signal based on clock ratios

An automatic phase detection circuit for generating an internal synchronization signal when two clock input signals achieve a certain phase relationship. No external reference signal is required. The logic state of one clock is sampled on the active edge of the other clock and stored in a shift register. The content of the shift register is compared to a pre-defined signature and a sync signal is generated when the content matches the pre-defined signature. A mask register may be used to define which bits of the shift register and pre-defined signature are compared.

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Fremont, CA, United States of America

Bharat K Daga