International Business Machines Corporation

Bharat D Rathi

Kevin Patrick McAuliffe

Manoj N Kumar

Philip Heidelberger

Peter Anthony Franaszek

Gregory Francis Pfister

Howard Thomas Olnowich

David Alson George

Thomas Norman Barker

David Joseph Wisneski

Sandra Johnson Baylor

Ambuj Goyal

Vern A Norton

Terry L Borden

Anujan Mangala Varma

William K Kelley

Iderpal S Narang

A multi-stage architecture for providing a single switching component in multiplicity to create a single network capable of performing a multiplicity of functions. One function of the disclosed network is to circumvent the traditional blocking problems in multi-stage networks by implementing ALTERNATE PATHS between devices within the same network. This permits a non-blocked path between 2 devices to be found by rearrangeability--the act of trying or searching different alternate paths until a non-blocked connection is established. A second network function permits a special high priority mode of transfer which will guarantee that the connection will be made to an idle device as rapidly as possible.

Multi-function network

A parallel query processing system comprises a front end processor, a query processing complex attached to the front end processor, and a database on a data repository attached by a first path to the front end processor, and by one or more additional paths to one or more slave processors within the query processing complex. An external operations command processor within the front end processor quiesces database managers in the slave processors to permit maintenance operations by the front end processor, and restarts the slave processors in read-only mode after maintenance operation completion. A splitter/scheduler function in a master processor within the query processor complex receives complex read-only queries from the front end processor, splits them into query elements, schedules the query elements for execution on the slave processors and recombines the execution results to be sent back to the front end processor.

System for parallel processing of complex read-only database queries

A directory-based protocol is provided for maintaining data coherency in a multiprocessing (MP) system having a number of processors with associated write-back caches, a multistage interconnection network (MIN) leading to a shared memory, and a global directory associated with the main memory to keep track of state and control information of cache lines. Upon a request by a requesting cache for a cache line which has been exclusively modified by a source cache, two buffers are situated in the global directory to collectively intercept modified data words of the modified cache line during the write-back to memory. A modified word buffer is used to capture modified words within the modified cache line. Moreover, a line buffer stores an old cache line transferred from the memory, during the write back operation. Finally, the line buffer and the modified word buffer, together, provide the entire modified line to a requesting cache.

Optimum write-back strategy for directory-based cache coherence protocols

An interconnection network management architecture for use with a large shared memory multiprocessor computing system including a plurality of processors and a plurality of separately addressable main memory modules. Two parallel, interconnection networks are provided each capable of interconnecting any processor to any memory module, and each having different latency characteristics. A Hot-Spot detection mechnaism is associated with each main memory module for detecting when a particular address in that module has become a Hot Spot and includes a first memory for storing all detected Hot Spots. A diverter element is associated with each processor for selectively routing memory requests over either the first or second memory network contingent on its status as a Hot Spot. A second memory is included in each diverter element for storing all Hot Spots detected by the detector elements. A control mechanism determines if any current main memory address is a listed Hot Spot within the second memory and, if so, causes the main memory reference to be transmitted to the memory system over a selected interconnection network. Another component of this mechanism determines if a particular address has been accessed a sufficient number of times within a given timeframe to be deemed a Hot Spot and removes Hot Spots from both the first and second memories when necessary.

Hardware mechanism for automatically detecting hot-spot references and

In a data processing system of the type including a plurality of processing elements interconnected with each other and with a plurality of memory elements by an interconnection means, a method is provided for accommodating the accessing of a selected memory location in a selected one of the memory elements by at least one requesting processing element to read data stored thereat. The method thereby permits the communication of information between the plurality of processing elements. The method comprising the steps of: sending, from the requesting processing element to the selected memory element via the interconnecting means, a directive including (1) the address of the selected memory location, (2) a comparison value, and (3) an identification of the requesting processing element sending the directive; reading in the selected memory element the data stored at the selected memory location; comparing in the memory element the read data with the comparison value; notifying the requesting processing element via the interconnection means if the read data matches the comparison value; storing the directive in the selected memory element if the read data does not match the comparison value; and repeating the reading, comparing, and notifying steps each time the data in the selected memory location is altered.

Data processing system incorporating a memory resident directive for

A method and apparatus used to detect errors in a signal transmitted over a single wire. All transient errors are detected when the effect of the transient lasts for at least one cycle and not more than five cycles. Transient errors of longer duration will be detected if the level of the original signal at the start of the transient is different from that at the end of the transient. Stuck faults will be deleted if one onset of the stuck fault causes the level of the signal to change. Redundancy is incorporated by introducing redundant transitions in the signal on the same wire. This requires the successive transitions in the original signal to be at least three cycles apart. If a transition is viewed as a binary one and the absence of a transition as a binary zero then each binary one is replaced with the sequence 'one-one-one' (overwriting subsequent zeros), and keeping each zero as the single bit 'zero'. Upon decoding, each group of three transitions is converted to a single transition. Signals having more than or less than three consecutive transitions which are not in multiples of three are determined to be in error.

Method and apparatus for detecting transient errors

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Mahopac, NY, United States of America

Bharat D Rathi