Intel Corporation

Cadence Design Systems, Inc.

Vlsi Technology, Inc.

Bharat Bhushan

Edward Thomas Grochowski

John H Crawford

Vinod Sharma

Harsh Dev Sharma

Rajeev Srivastava

Mithunjoy Parui

Christopher G Arcus

Paul D Ta

Kenneth R Smits

Albert Lee

Srinivas R Kommoori

Vivek Joshi

Mahadevamurty Nemani

Eric S Gayles

Debashree Ghosh

Po-chiang Albert Lee

Srivinas R Kommoori

Systems and methods to optimize a layout based on the yield analysis is disclosed. The method includes generating an integrated circuit layout having two or more layers of wire interconnect to form net segments and having one or more via contact layers to couple net segments in the wire interconnect together. The method further includes performing a yield analysis of the net segments in the integrated circuit layout and displaying the net segments with a visual depiction of the yield analysis using multiple levels of opacity to reflect yield scores of the net segments in the integrated circuit layout.

Visual yield analysis of intergrated circuit layouts

According to various embodiments of the invention electronic circuit design information can be presented to a designer by determining an electronic circuit comprising at least two gates and by determining a distance of one gate relative to another gate in a stage. A visual indicator for the stage can be calculated based on the distances between at least two gates in the stage. The visual indicator can then be displayed. The visual indicator can be a color and the relative distance can be indicated by brightness, hue or saturation, etc. Alternatively, the visual indicator can be a pattern and the relative distance between at least two gates can be indicated by darkness of the pattern.

Graphical user interface for prototyping early instance density

Disclosed are methods, systems and apparatus for automatically placing decoupling capacitors in an integrated circuit to compensate for voltage drops that might otherwise occur in a power grid. In one embodiment of the invention, the method includes generating one or more regions of the integrated circuit design, with each region having one or more cells, determining an amount of decoupling capacitance required in each region of the integrated circuit design by analyzing each cell in the region, and adding sufficient decoupling capacitor cells to the region to compensate for the potential voltage drop.

Automatic placement of decoupling capacitors

A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in a redundant form to also subtract numbers received in redundant form, including numbers received from a bypass circuit. A non-propagative comparator circuit is then used to compare a given value with a result from the arithmetic circuit to determine if the result is equal to the given value. All of the operations described above can be accomplished without propagating carry signals throughout the circuitry. The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit. This adjustment causes the arithmetic circuit to generate a valid outcome in redundant form as a result of a subtraction operation if the arithmetic operation is subtraction. Then the result is compared to a given value using a non-propagative comparator to determine equality or inequality of the result to the given value.

Method and apparatus for performing single-cycle addition or subtraction and comparison in redundant form arithmetic

The present invention provides an efficient method for bypassing outputs while in redundant form to an arithmetic circuit that is capable of adding or subtracting numbers in redundant from and comparing the magnitudes of numbers received in redundant form for equality and inequality relationships. For one embodiment of the invention, an arithmetic circuit subtracts numbers received in redundant form and compares the result to zero represented in redundant form without carry propagation. In parallel with the subtraction and comparison, the most significant bits of each number received in redundant form are generated and compared for equality, and a carry-out is generated for the subtraction. These results are combined by magnitude comparison logic to produce a magnitude comparison for the numbers received in redundant form.

Method and apparatus for a fast comparison in redundant form arithmetic

Method and apparatus for performing equality comparison in redundant form arithmetic

A method and apparatus for adding numbers represented in redundant form or for subtracting numbers received in redundant form and for comparing results in redundant form for equality to an expected value. A redundant arithmetic circuit performs an arithmetic operation on operands received in redundant form to generate a result represented in redundant form. A comparator circuit is coupled with the arithmetic circuit to receive the result in redundant form and to perform an equality comparison of the result to the expected value, and to indicate the truth of said equality comparison independent of carry signal propagation from the least significant digit to the most significant digit.

Method and apparatus for performing subtraction in redundant form arithmetic

A cache memory organized into banks of subarrays includes repeaters for connecting to the data provided by the subarrays to a global data bus. The repeaters comprise a logic gate providing either a NAND or NOR function coupled in series with an inverter. The logic gate has a first input connected to receive a first logic value of a bus line, and a second input coupled to receive data output from a subarray. The inverter drives the first logic value onto the bus line when the cache bank subarray is inactive, and drives the data value from the subarray onto the bus line when the cache bank subarray is activate.

On-die cache memory with repeaters

Architecture for a cache fabricated on a die with a processor including a plurality of cache banks, each containing a plurality of storage cell subarrays, the cache banks being arranged in physical relationship to a central location on the die that provides a point for information transfer between the processor and the cache. A data path provides synchronous transmission of data to/from the cache banks such that data requested by the processor in a given clock cycle is received at the central location a predetermined number of clock cycles later regardless of which cache bank in the cache the data is stored.

Cache architecture for pipelined operation with on-die processor

A domino circuit may be provided with additional keeper transistors that are selectively activated when one of the input transistors in a logic structure has a low or inactive signal applied to it during the evaluation stage. Thus, the potential of the output node of the domino circuit may be maintained, improving the soft error rate.

Data driven keeper for a domino circuit

A fast translation look-aside buffer for translating a linear address R,&equals;A&plus;B to a physical address, where A and B are two N bit operands. Inputs to the translation look-aside buffer are the n highest-order bits of A and B, where n<N, and the carry-out term from the sum of the first N&minus;n bits of A and B. The TLB may provide a hit without the need for the sum of A and B.

Translation look-aside buffer utilizing high-order bits for fast access

A domino logic circuit includes a first domino gate that evaluates one or more inputs responsive to a clock signal, a reset gate, and a second domino gate having a first input coupled to the output of the first domino gate. A first input of a reset gate is coupled to the output of the first domino gate, with a second input of the reset gate being coupled to the output of the second domino gate. The reset gate outputs a precharge signal coupled to a second input of the second domino gate when the second domino gate is discharged and the output of the first domino gate changes state such that a high-to-low transition occurs at the first input of the second domino gate.

Contention-free, low clock load domino circuit topology

A ring-style, multi-stage VCO of a phase lock loop circuit includes two or more differential amplifier stages. The phase lock loop includes a lowpass filter connected between a control voltage terminal and a voltage-to-current converter stage, which includes a first source-follower MOS transistor M1 with a source resistor R1 and a diode-connected MOS transistor M2 connected to its drain terminal. A current-source MOS transistor M8 has a gate terminal connected to the drain of the first MOS transistor M1 such that the transistor M8 mirrors current of transistor M1. A diode-connected transistor M9 has its gate terminal and its drain terminal connected together and also to the drain terminal of transistor M8. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN.sub.-- terminal. The drain terminal of MOS transistor M4 provides an OUT.sub.-- signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the drain terminal of transistor M9.

Low noise low voltage phase lock loop

A ring-style, multi-stage VCO of a phase lock loop circuit includes two or more differential amplifier stages. The phase lock loop includes a lowpass filter connected between a control voltage terminal and a voltage-to-current converter stage, which includes a first source-follower MOS transistor M1 with a source resistor R1 and a second diode-connected MOS transistor M2 connected to its drain terminal. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN.sub.-- terminal. The drain terminal of MOS transistor M4 provides an OUT.sub.-- signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the voltage control input terminal of the phase lock loop.

Growing community of inventors

Cupertino, CA, United States of America

Bharat Bhushan