Texas Instruments Corporation

Bharadwaj Parthasarathy

Robert Floyd Payne

Haydar Bilhan

Sucheendran Sridharan

James E Nave

Vijay Kumar Pathak

Srinath Devalapalli

A bit stream includes playback data having an associated clock rate and a variable reference clock that is synchronized to the bit stream. A playback clock recovery signal and a data recovery signal are generated in response to the received reference clock. A playback clock frequency signal is generated in response to the playback clock recovery signal. A recovered playback clock is generated by using a divide by M divider, wherein the value of M used by the divide by M divider is determined in response to a programmable multiple of the clock rate associated with the playback information.

Shared-PLL audio clock recovery in multimedia interfaces

The present invention facilitates clock and data recovery () for serial data streams () by providing a mechanism that can be employed to maintain a fixed tracking capability of an interpolator based CDR circuit () at multiple data rates (e.g.,). The present invention further provides a wide data rate range CDR circuit (), yet uses an interpolator design optimized for a fixed frequency. The invention employs a rate programmable divider circuit () that operates over a wide range of clock and data rates (e.g.,) to provide various phase correction step sizes (e.g.,) at a fixed VCO clock frequency. The divider () and a finite state machine (FSM) () of the exemplary CDR circuit () are manually programmed based on the data rate (). Alternately, the data rate may be detected from a recovered serial data stream () during CDR operations (on-the-fly) utilizing a frequency detection circuit () to automatically program the divider () and FSM () to provide CDR circuit operation at the nearest base clock rate ().

Interpolator based clock and data recovery (CDR) circuit with digitally programmable BW and tracking capability

The present invention provides a robust solution to the task of re-aligning data at the transmit end of a fiber optic or other high performance serial link, and also offers flexibility in the circuit board design approach. A high performance analog phase locked-loop circuit is used to simultaneously provide clock recovery for multiple bit streams. The power dissipation required to perform clock recovery is thereby reduced to a fraction of that required in conventional transmit systems. This analog phase locked loop produces plural phase output signals. An output multiplexer selects one phase for use in electrical to optical conversion.

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Plano, TX, United States of America

Bharadwaj Parthasarathy