Advanced Micro Devices Corporation

Other

Globalfoundries Inc.

Spansion Llc.

Advanced Micro Technologies, Inc.

Bhanwar Singh

Ramkumar Subramanian

Bharath Rangarajan

Khoi A Phan

Michael K Templeton

Sanjay K Yedur

Bryan K Choo

Christopher F Lyons

Marina V Plat

Srikanteswara Dakshina-Murthy

Carmen L Morales

Arvind Halliyal

Steven C Avanzino

Angela Tai Hui

Kouros Ghandehari

Subhash Gupta

Cyrus E Tabery

Gilles Amblard

Luigi Capodieci

Ursula Q Quinto

Iraj Emami

Scott Allan Bell

Calvin T Gabriel

Che-Hoo Ng

Fei Wang

Paul Raymond Besser

Todd P Lukanc

Shekhar Pramanick

Susan H Chen

Bruno M LaFontaine

Jason Phillip Cain

Minh Van Ngo

James K Kai

Matthew S Buynoski

Dawn M Hopper

Darrell M Erb

Wenge Yang

Carl P Babcock

James Jiahua Yu

Robert J Chiu

Subash Gupta

Sarah McGowan

Joerg Reiss

Catherine B Labelle

Cristina Cheung

Zoran Krivokapic

Junwei Bao

Jeffrey Allan Shields

Christy Mei-Chu Woo

Simon S Chan

Nicholas H Tripsas

Amit P Marathe

Christopher A Spence

Joong Jeon

Uzodinma Okoroanyanwu

Joyce S Oey Hewett

Kathleen R Early

Wen Yu

Diana M Schonauer

Jeff P Erhardt

Ercan Adem

David H Matsumoto

Chris Haidinyak

Ciby Thuruthiyil

Wolfram Grundke

Ahmad Waleh

Alden R Acheta

Harish Kumar Bolla

Mutya Vicente

Shobhana R Punjabi

Shekhan Pramanick

Winny Stockwell

Qiaolin Zhang

Luigi Capodiece

Wolfram Porsche

Jay Bhakta

Alvin M Dangca

Itty Matthew

The subject invention provides systems and methods that monitor and/or control turbulence of an immersion medium. The systems and methods relate to computer controlled techniques that reduce effects of immersion medium flow due to a liquid temperature gradient. According to an aspect of the subject invention, a number of temperature measurements of the immersion medium are obtained, and the temperature measurements are utilized to generate a gradient map of the immersion medium. By way of illustration, the temperature measurements can be made via wireless temperature sensors. The gradient map can be utilized to understand the stability of the immersion medium. According to an aspect of the subject invention, instability identified with the gradient map can be mitigated.

Systems and methods that control liquid temperature in immersion lithography to maintain temperature gradient to reduce turbulence

A method of correcting a lithographic mask is disclosed. The method can include detecting a location of the mask that corresponds to a wafer location having a structure that is printed with a larger than desired dimension and reducing a thickness of at least a portion of a mask feature corresponding to the wafer structure to locally increase transmissivity of the mask feature.

Method of lithographic mask correction using localized transmission adjustment

The present invention provides for a system and method for regulating and monitoring heat dissipation of an integrated circuit by employing a heat regulating device with a thermal structure net work assembly. Each thermal structure can act as a heat conducting pathway for inducing heat into and/or dissipating heat away from the integrated circuit, thus creating a more uniform temperature gradient across the semiconductor body.

Mitigating heat in an integrated circuit

A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold. A sequence of etches transfer and combine the via features from the first imaging layer with the trenches from the second imaging layer to create the dual damascene openings within the dielectric layer.

System and method for imprint lithography to facilitate dual damascene integration with two imprint acts

The claimed subject matter provides a system and/or a method that facilitates utilizing a resolution enhancement for a circuit feature. A scanning electron microscope component () can provide at least one two-dimensional image of the circuit feature. An image analysis engine () can analyze the two-dimensional image. An advanced process control (APC) engine () can generate at least one instruction for at least one of a feed forward control and a feedback control and a process component () can utilize the at least one instruction to minimize an error.

Advanced process control framework using two-dimensional image analysis

Disclosed are methods for eliminating and/or mitigating the formation of footing and/or T-tops in a resist pattern. A substrate with or without an antireflective coating layer may be treated with an acidic composition prior to the formation of a resist layer. The acid treatment prevents the loss of photo generated acid from the resist by either quenching and/or neutralizing the bases, and thereby reduces the formation of footing. The surface of a resist layer which has been irradiated may be treated with an acidic composition prior to post-exposure bake. The acid treatment prevents the loss of photo generated acid from the resist by either compensating for the evaporation and/or neutralization of the bases and thereby prevents the formation of T-tops.

Surface treatment with an acidic composition to prevent substrate and environmental contamination

The subject invention provides a system and method for improving the process margin of a lithographic imaging system. The process margin improvement is achieved through the novel placement of discrete assist features and/or the use of forbidden pitches and specific pitch orientations. Novel geometries are utilized, which take advantage of line-end pull back and/or a lack of resolution of pitches perpendicular to an axis of a dipole illumination source. The strategic placement of a series of discrete scatterbar segments on a mask near positions of critical features, such as, for example, contacts, mitigates resist residue that can result from the use of a contiguous scatterbar.

Process margin using discrete assist features

A system and method are provided to facilitate dual damascene interconnect integration in a single imprint step. The method provides for creation of a translucent imprint mold with three-dimensional features comprising the dual damascene pattern to be imprinted. The imprint mold is brought into contact with a photopolymerizable organosilicon imaging layer deposited upon a transfer layer which is spin coated or otherwise deposited upon a dielectric layer of a substrate. When the photopolymerizable layer is exposed to a source of illumination, it cures with a structure matching the dual damascene pattern of the imprint mold. A halogen breakthrough etch followed by oxygen transfer etch transfer the vias from the imaging layer into the transfer layer. A second halogen breakthrough etch followed by a second oxygen transfer etch transfer the trenches from the imaging layer into the transfer layer. A dielectric etch transfers the pattern from the transfer layer into the dielectric layer. A metal fill process then fills the dual damascene openings of the dielectric layer with metal.

System and method for imprint lithography to facilitate dual damascene integration in a single imprint act

A mask is provided to be used with nanoprint lithography processes to facilitate reproduction of small features required for the production of integrated circuits. A translucent substrate is provided along with one or more three-dimensional features that include one or more vertical sidewalls. An absorbing material is deposited upon one or more of the vertical sidewalls so that light in an incident direction to an upper surface of the substrate will be absorbed by the absorbing material, resulting in light blocking features. One or more horizontal surfaces are formed upon one or more of the three-dimensional features, which allow light rays to exit a lower surface of the substrate unobstructed by the absorbing material.

Mask having sidewall absorbers to enable the printing of finer features in nanoprint lithography (1XMASK)

In fabricating an electronic structure, a substrate is provided, and a first barrier layer is provided on the substrate. A germanium thin film diode is provided on the first barrier layer, and a second barrier layer is provided on the germanium thin film diode. A memory device is provided over and connected to the second barrier layer.

Thin film germanium diode with low reverse breakdown

The disclosed embodiments reduce across-chip performance variation through non-contact electrical metrology. According to a feature is a process control system that includes a component that measures transistor electrical performance in a product wafer. Also included in the system is a mapping component that converts the transistor performance into exposure dose values and a process tool that communicates the exposure dose value to a scanner. The exposure dose value is fed back for optimization of future chip exposures. The disclosed embodiments directly optimize transistor performance, thus controlling an important parameter in many integrated circuits.

Scanner optimization for reduced across-chip performance variation through non-contact electrical metrology

The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate compensating for retrograde feature profiles on an imprint mask. An aspect of the invention generates feedback information that facilitates control of imprint mask feature profile via employing a scatterometry system to detect retrograde feature profiles, and mitigating the retrograde profiles via a spacer etchback procedure.

Feedback control of imprint mask feature profile using scatterometry and spacer etchback

The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate the reduction of line-edge roughness (LER) during gate formation in an integrated circuit. Systems and methods are disclosed for improving critical dimension (CD) of photoresist lines, comprising a non-lithographic shrink component that facilitates mitigating LER, and a trim etch component that facilitates achieving and/or restoring a target critical dimension.

Combination of non-lithographic shrink techniques and trim process for gate formation and line-edge roughness reduction

Disclosed are photolithographic systems and methods, and more particularly systems and methodologies that enhance imprint mask feature resolution. An aspect generates feedback information that facilitates control of imprint mask feature size and resolution via employing a scatterometry system to detect resolution enhancement need, and decreasing imprint mask feature size and increasing resolution of the imprint mask via a trim etch procedure.

Imprint lithography mask trimming for imprint mask using etch

The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate compensating for imprint mask critical dimension error(s). An aspect of the invention generates feedback information that facilitates control of imprint mask critical dimension via employing a scatterometry system to detect imprint mask critical dimension error, and mitigating the error via a spacer etchback procedure.

Post fabrication CD modification on imprint lithography mask

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Morgan Hill, CA, United States of America

Bhanwar Singh