Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Bhanushankar Doni

Raghavendra Gopalakrishnan

Manohar Srinivasaiah

Raghavendra Gopalkrishnan

Harish Gajula

Pratik Bhatt

Technology is disclosed herein for multi-stage data compaction. In a first data compaction stage valid data fragments from source erase block(s) are programmed into a destination erase block at two bits per memory cell. In a second data compaction stage additional valid data from the source erase block(s) is programmed into the destination erase block at two bits per memory cell. In this second stage, the same physical pages of memory cells in the destination erase block may be programmed such that each memory cell in the destination erase block is programmed to four bits.

Multi-stage data compaction in NAND

A data storage device, in one implementation, includes a memory device having Single Level Cell (SLC) blocks and Multi-Level Cell (MLC) blocks, such as Triple Level Cell (TLC) blocks. If a SLC block is determined to have errors, the SLC block is reallocated as a TLC block. In some implementations, the TLC block is used to store TLC cold data.

Block budget enhancement mechanisms for memory

Technology is disclosed herein for efficient use of volatile memory that is used for accumulating parity data of user data being written to non-volatile memory cells. A memory controller may replace primary parity in a first portion of a parity buffer with data other than primary parity while a second portion of the buffer is still being used to store the primary parity. Therefore, the memory controller smartly re-uses the parity buffer, which makes efficient use of the volatile memory. In one aspect, a memory controller accumulates secondary parity for the user data in a first portion of the parity buffer while a second portion of the parity buffer is still being used to store the primary parity. The memory controller may compute the secondary parity from present content of the first portion of the parity buffer and primary parity presently stored in the second portion of the buffer.

Smart re-use of parity buffer

An apparatus comprising non-volatile memory is configured to access a selected unit of encoded SLC data in the non-volatile memory during a first programming phase of a process of folding data stored at a single bit per memory cell to data stored at multiple bits per memory cell. The apparatus recovers the selected unit of SLC data based on redundancy data formed from units of SLC data that data include the selected unit of SLC data. The apparatus saves the recovered selected unit of SLC data to memory. The apparatus uses the saved recovered unit of SLC data during a second programming phase of folding the data stored at a single bit per memory cell to the data stored at multiple bits per memory cell, thereby saving considerable time in not having to again recover the SLC data using the redundancy data.

Growing community of inventors

Bengaluru, India

Bhanushankar Doni