Atrenta, Inc.

Bhanu Kapoor

Debabrata Bagchi

Sanjay Churiwala

Joy Banerjee

Nitin Sharma

A method, system and computer program product for generating and verifying the correctness of isolation logic modules in design of integrated circuits (ICs). The method disclosed generates an isolation logic module for each power domain specified by a user, instantiates the generated module in a pre-determined wakeup domain, and then simulates shutdown conditions to ensure the correctness of the generated isolation logic module. The isolation logic is generated based on user-defined voltage constraints.

Method, system, and computer program product for generating and verifying isolation logic modules in design of integrated circuits

A method for optimization of clock gating in integrated circuit (IC) design. Clock gating techniques are very useful in reducing the electrical power consumed by an IC. A general method for identifying registers that are candidates for clock gating is presented. Furthermore, a determination is made regarding which of the candidate registers to clock gate in order to achieve optimal power and IC area savings. The determination is based on switching activity of the candidate registers.

Method of optimization of clock gating in integrated circuit designs

Method, system and computer program product for generating and verifying isolation logic modules in design of integrated circuits

Level shifter modules, used in integrated circuits (ICs), are automatically inserter and their correctness verified. A level shifter module for signals crossing voltage domains is generated, and instances thereof are inserted in a pre-determined voltage domain. Several checks ensure the correctness of the inserted level shifter module. The level shifter modules are instantiated based on user-defined voltage constraints.

Method, system, and computer program product for automatic insertion and correctness verification of level shifters in integrated circuits with multiple voltage domains

Identification and implementation of clock gating in the design of an integrated circuit (IC) is performed with automated assistance. Electrical power consumption is reduced by clock gating. The automated assistance identifies registers that are candidates for clock gating, and highlights, in the IC design, registers associated with a gated clock domain and the logic blocks driven by these registers.

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Richardson, TX, United States of America

Bhanu Kapoor