Texas Instruments Corporation

Infrared Integrated Systems Limited

The Secretary of State for Defence in Her Britannic Majesty's Government

Gec-marconi Limited

Bhajan Singh

John Fox

Stephen George Porter

Andrew J Pickering

Derek Colman

Richard Ward

Tom Leslie

Susan M Simpson

Vipul Raithatha

David Harry Broughton

Sean N Batty

Antonio David Sebastio

Graham Robert Jones

Thomas Leslie

Vincent Considine

David G Haigh

A data transfer circuit is provided for sending digital data at high rates across short but significant distances within an integrated circuit. The data is sent on parallel conductors that are divided into a number of groups. At the receiving end, a multiplexer selects each of the groups in turn and presents them at a set of conductors that are the same in number as one of the groups. At the transmitting end, a data marshalling circuit takes the bitstream to be transmitted and places it on the conductors in a particular redundant fashion so that the bitstream appears to advance across the set of outputs of the multiplexer. That is particularly useful where those outputs are presented to a pre-emphasis filter and line driver. The apparent data rate can be changed by making two or more of the groups of conductors have identical data.

Data transfer circuit

Methods and apparatus are disclosed to track and hold a voltage. An example track and hold circuit comprises a first electronic switch, a second electronic switch, and a current mode logic amplifier.

Track and hold circuit

There is provided a method for Loss of Signal Built In Self Test, and corresponding apparatus comprising: a loopback driver for receiving test signals, and for directing the test signals to at least one of a first output of the loopback driver and a second output of the loopback driver; a Digital to Analogue Converter DAC connected to the loopback driver for controlling the amplitude of the data input signals transmitted by the loopback driver; and coupling means for directing the scaled signals to a Loss of Signal detector. Also provided is a method for testing the hysteresis thresholds of an ACJTAG module, and corresponding apparatus comprising a loopback driver for receiving data test signals, and for directing the test signals to at least one of a first output of the loopback driver and a second output of the loopback driver; a Digital to Analogue Converter DAC connected to the loopback driver for controlling the amplitude of the data input signals transmitted by the loopback driver; and coupling means for directing the scaled signals to the ACJTAG block.

Built in self test

A receiver equalizer with a first equalizer unit having a basic equalizer stage and a negative impedance cell connected to the basic equalizer stage. Preferably the negative impedance cell has a pair of back to back transistors, and connected thereto a parallel resistor capacitor RC network. The basic equalizer stage has a pair of current sources; a pair of transistors arranged as a differential pair, each transistor connected to a different one of the current sources; and a degeneration impedance connected in between the two current sources, and the transistors, wherein the negative impedance cell is connected across the outputs of the pair of transistors.

High bandwidth high gain receiver equalizer

There is provided a clock phase interpolator comprising a pair of output nodes, at least three complementary clock signal inputs, an equal plurality of current sources, and an equal plurality of clock switching sections. Each clock switching section is connected to switch, under the control of a complementary clock signal on a respective one of the complementary clock signal inputs, the current provided by a respective one of the current sources between the two output nodes. The current sources are controllable to provide interpolation between signals on the complementary clock signal inputs. Also provided is a clock phase interpolator comprising a pair of output nodes, two complementary clock signal inputs, an equal plurality of current sources, an equal plurality of clock switching sections. Each clock switching section is connected to switch, under the control of a complementary clock signal on a respective one of the complementary clock signal inputs, the current provided by a respective one of the current sources between the two output nodes. The current sources are controllable to provide interpolation between signals on the complementary clock signal inputs, and each load comprises an integrator.

Triangulating phase interpolator

A method of testing resistance bolometer arrays involves applying different voltages to different bolometers so as to produce a detectable difference between adjacent bolometers under normal conditions. The voltages may be applied in a recognizable pattern so that faults can be readily identified from a visual display of the array.

Testing resistance bolometer arrays

A two dimensional array of resistive bolometers (B) is arranged in rows and columns. Amplifiers (A , A etc) amplify signals obtained from the bolometers. Instead of providing one amplifier per column, a smaller number of amplifiers is used each of which is connected to a plurality of column sense lines (L) via a multiplexer (M , M etc).

Method of multiplexing column amplifiers in a resistive bolometer array

A signal processing technique applied to the readout of two-dimensional detector arrays provides a dynamic correction mechanism for the varying offsets of the different elements of the array. The outputs of the elements are supplied to an offset correction circuit operative to compensate for the differences in the d.c. or low frequency outputs from a predetermined voltage wherein a fraction of the difference is subtracted at each successive cycle to gradually reduce the difference.

Dynamic offset correction in detector arrays

An all-digital phase locked loop circuit is described in which a numerically controlled oscillator is driven at a multiple of a required output frequency; a counter is provided to divide the output frequency of the oscillator by the multiple; an analogue to digital converter is provided to sample an input signal having the required frequency, and the frequency of the numerically controlled oscillator provides the sampling rate of the converter.

Growing community of inventors

Birmingham, United Kingdom

Bhajan Singh