Xilinx, Inc.

Bhaarath Kumar

Sarosh Azad

Tomai Knopp

Sarosh I Azad

A memory management unit circuit includes a plurality of ports with a plurality of translation buffer units. Each translation buffer unit includes a translation lookaside buffer circuit and a translation logic circuit configured to perform virtual to physical address translation using the translation lookaside buffer circuit. A translation lookaside buffer circuit prefetch logic circuit monitors virtual memory access requests received at the corresponding port of the memory management unit circuit and detects satisfaction of at least one trigger condition. In response, address translation prefetch requests are generated. A control circuit transmits the address translation prefetch requests to a physical memory circuit and receives address translation data for populating the translation lookaside buffer.

Memory management unit with prefetch

Virtual memory pre-fetch requests are generated for a virtual memory and a multiple port memory management unit (MMU) circuit. Virtual memory access requests sent to a particular port of the MMU circuit are monitored. In response to the satisfaction of a trigger condition, virtual memory pre-fetch requests are generated and transmitted to the MMU circuit using the particular port. Physical access requests from the MMU circuit are monitored for physical addresses corresponding to the virtual memory pre-fetch requests. The physical access requests corresponding to the virtual memory pre-fetch requests are filtered.

Memory pre-fetch for virtual memory

The disclosure describes a circuit arrangement that includes a master circuit and a slave circuit. The master circuit generates transactions, and the slave circuit generates responses to the transactions from the master circuit. A first circuit is coupled between the master circuit and the slave circuit. The first circuit determines for each transaction from the master circuit whether the slave circuit generates an expected number of responses within a timeout period. For each transaction for which the slave circuit does not generate the expected number of responses within the timeout period, the first circuit generates and transmits the expected number of responses to the master circuit.

Circuit arrangement with transaction timeout detection

An apparatus for communication using a master-slave communication protocol includes a master circuit and a slave circuit configured to communicate with each other using a master-slave communication protocol. The apparatus also includes an interface circuit coupled to the master and slave circuits. In response to a first control signal having a first value, the interface circuit forwards messages received from the master circuit to the slave circuit and forwards responses received from the slave circuit to the master circuit. In response to the first control signal having a second value, the interface circuit prevents messages received from the master circuit from being forwarded from the master circuit to the slave circuit.

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Fremont, CA, United States of America

Bhaarath Kumar