Altera Corporation

Bezhad Nouban

Khusrow Kiani

Janusz K Balicki

Bahram Ahanin

William W Leong

Ken-Ming Li

A method and apparatus for reducing the number of programmable architecture elements required for implementing a look-up table in a programmable logic device. At least one logic function to be performed by the look-up table is chosen. An output state is determined for each set of inputs to the look-up table, the output state being an array of outputs of the look-up table. Each output state is made up of responses of the chosen logic functions to a particular set of input variables. Identical output states are formed into groups. Selected groups of the output states which do not require programmable architecture elements are eliminated. A programmable architecture element is then assigned for each remaining group of output states.

Method and apparatus for reducing the number of programmable

A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.

Programmable logic device having fast programmable logic array blocks

Flexible configuration logic array block for programmable logic devices

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Fremont, CA, United States of America

Bezhad Nouban