Texas Instruments Corporation

Betty S Mercer

Binghua Hu

Byron Lovell Williams

Scott Kelly Montgomery

Maxwell Walthour Lippitt, Iii

Timothy S Henderson

Alec James Morton

Clyde R Fuller

Joseph B Delaney

C Matthew Thompson

Erika Leigh Shoemaker

Laurinda W Ng

Byron Lovell Willaims

In a disclosed embodiment, a stacked capacitor () has bottom, middle and top metal electrode layers (A,B,C) interleaved with dielectric layers (A,B) conformally disposed within holes (A,B,C) in a protective overcoat or backend dielectric layer () over a top metal layer () of an integrated circuit (). A top electrode () contacts the top metal electrode layer (C). A bottom electrode () electrically couples an isolated part of the top metal electrode layer (C) through a bottom electrode via (A) to a first contact node (A) in the top metal layer () which is in contact with the bottom metal electrode layer (A). A middle electrode () electrically couples a part of the middle metal electrode layer (B) not covered by the top metal layer () through a middle electrode via (B) to a second contact node (B) in the top metal electrode layer (). The sidewalls of the top and middle electrode vias (A,B) are lined with insulating material to electrically isolate the metal electrode layer ends.

Multiple electrode layer backend stacked capacitor

An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend dielectric layer of an integrated circuit and depositing multiple layers of metal, each layer of metal electrically tied to an associated electrode. The method also includes alternately depositing multiple layers of dielectric between the multiple layers of metal and coupling a bottom layer of the multiple layers of metal to a contact node in a top metal layer of the integrated circuit.

Methods and devices for a high-k stacked capacitor

The present invention provides an interconnect for use in an integrated circuit, a method for manufacturing the interconnect, and a method for manufacturing an integrated circuit including the interconnect. The interconnect (), among other elements, includes a surface conductive lead () located in an opening formed within a protective overcoat (), and a barrier layer () located between the protective overcoat () and the surface conductive lead (), a portion of the barrier layer () forming a skirt () that extends outside a footprint of the surface conductive lead ().

Method for manufacturing an interconnect

Generally, and in one form of the invention a method for making a heterojunction bipolar transistor comprising the steps of forming a compound semiconductor material structure comprised of a plurality of layers, wherein at least one of the plurality of layers is comprised of a first material (e.g. GaAs 36) and at least one of the remaining of the plurality of layers is comprised of a second material (e.g. AlGaAs 32); and etching the layers comprised of the first material with an etchant that does not appreciably etch the layers of the second material is disclosed. A surprising aspect of this invention is that no additional etch stop layer was added in the material structure. Etchants were found that stop on the wide band gap emitter layer (e.g. AlGaAs) usually found in heterojunction bipolar transistors despite the similarity of the materials. An advantage of this method is that a reference point for timing subsequent etches is established at a point other than the top of the uppermost of the layers, thereby improving the accuracy with which the depth of the subsequent etching can be controlled. Improved etch depth accuracy directly relates to more producible and higher yield heterojunction bipolar transistor devices. Other devices, systems, and methods are also disclosed.

Compound semiconductor heterojunction bipolar transistor

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Richardson, TX, United States of America

Betty S Mercer