Lattice Semiconductor Corporation

Bertrand Leigh

Ju Shen

Hua Xue

Mike Ray

Chris West

Satwant Singh

Andrew S Deming

Rahulkumar Koche

James S Larsen

Daniel T Gardner

Systems and methods for management of remotely programmable, programmable logic devices (remote PLDs) are disclosed. An example system includes a remote PLD including a plurality of programmable logic blocks (PLBs) arranged in a PLD fabric and a programmable input/output (I/O) coupled to the PLD fabric. The remote PLD is configured to form a communications link between the remote PLD and a remote PLD management system node over a communications network via a communication module of the remote PLD or a host device configured to interface with the remote PLD over the programmable I/O. The remote PLD is configured to receive a protected configuration image from the remote PLD management system node over the communications link and programs the PLD fabric according to the protected configuration image.

Remote programming systems and methods for programmable logic devices

Systems and methods provide improved techniques directed to simultaneous switching output (SSO) noise, which for example may be applied during the programmable logic device design process. For example in accordance with an embodiment, a method of structuring simultaneous switching output (SSO) noise data for an electronic device includes collecting hardware data on SSO noise conditions; generating additional data on SSO noise conditions based on the hardware data; and structuring the hardware data and the additional data to form data tables for SSO noise calculations.

Simultaneous switching output noise estimation and reduction systems and methods

Systems and methods provide I/O signal placement algorithms, such as for a programmable logic device. For example, a performing input/output (I/O) signal placement to pins of an electronic device, in accordance with an embodiment, includes placing all pre-assigned I/O signals to their assigned pin locations; placing unassigned I/O signals to initial I/O pin locations; and performing a simulated annealing for the I/O signals placed at initial I/O pin locations, wherein the simulated annealing accounts for simultaneous switching output (SSO) noise requirements.

Input/output placement systems and methods to reduce simultaneous switching output noise

Program data generated by the host system to be used in programming one or more associated ISPLDs is converted using a first interface from a parallel data format to a serial data string and then transmitted serially to a second interface. In one embodiment, the first and second interfaces employ Universal Asynchronous Receiver/Transmitter (UARTs). The receiving unit converts the serial program data string to a parallel data byte which is then provided to the programming pins of the ISPLD desired to be programmed. Signals indicative of information relating to the operation of one or more of the ISPLDs associated with the host system may be provided to the host system via pin SDO of the asserted ISPLD. In this manner, embodiments in accordance with the present invention may utilize a two-wire transmission scheme, and thus two-wire interfaces, to facilitate programming of the associated ISPLDs. Having the capability to utilize a two-wire transmission scheme, in turn, allows ISPLDs in accordance with the present invention to be programmed using wired transmission schemes such as, for instance, twisted pair and coaxial, as well as wireless transmission schemes, such as, for instance, radio frequency (RF) and infrared radiation (Ir).

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Portland, OR, United States of America

Bertrand Leigh