Cypress Semiconductor Corporation

Draker, Inc.

Advanced Micro Devices Corporation

Silicon Laboratories Inc.

Kld Energy Nano-grid Systems, Inc.

Solar Power Technologies, Inc.

Bertrand Jeffery Williams

Kamal Dalmia

Nathan Y Moyal

Sam Brandon Sandbote

Terry D Little

Paul H Scott

Shawn R McCaslin

Mohammad J Navabi

Mark J Marlett

Timothy D Jordan

Steve Meyers

Eric N Mann

Michael L Duffy

Steven C Meyers

Gang Yuan

Sean Foley

Brian G Kirkland

Stanley Wilson

Phillip J Kruczkowski

Jaideep Prakash

Sua-Ki Stephanie Sculley

Ronald L Treadway

Victor Sauers, Ii

Phil Kruczkowski

Bret Allan Raymis

In one embodiment, an apparatus includes: a replica sampler circuit to sample a first voltage that is based on a reference voltage, the replica sampler circuit to at least approximate a non-linearity of a bias generator. The replica sampler circuit may include: a switch circuit, when enabled, to pass the first voltage; and a capacitor coupled to the switch circuit, the capacitor to be charged by the first voltage. The apparatus also may include a comparator coupled to the replica sampler circuit, the comparator having a first input terminal to receive the sampled first voltage and a second input terminal to receive the reference voltage, where the comparator is to output a first signal having a first value when the sampled first voltage departs from the reference voltage by at least a threshold amount, to cause a refresh of at least a portion of the bias generator.

Adaptive refresh rate generator

A pumpjack is operated continuously over a sequence of two adjacent pump stroke cycles, by energizing an electric motor to operate the pumpjack over a first pump stroke cycle according to a motor speed profile over a plurality of discrete control periods within the cycle, while receiving sensory feedback from one or more sensors. In response to the feedback, and while continuing to operate the pumpjack, one or more speed adjustments are made to specific control periods, so as to alter the motor speed profile while continuing to operate the electric motor to drive the pump jack. The intra-cycle control optimizes flow while reacting to detrimental and changing conditions.

Intra-stroke cycle timing for pumpjack fluid pumping

A converter unit to improve overall recovered power in a photovoltaic array configuration. Each photovoltaic panel in the photovoltaic array may be coupled to a respective converter unit, which may include a controller to sense an output voltage and output current produced by the solar panel, and manage the output voltage of a corresponding power converter to optimize and regulate the resultant bus voltage to a point which reduces overall system losses, maintains a low loss condition, and removes series-string non-idealities when the panels are series connected. The controller may also adapt to output condition constraints. Instead of single-port regulation, a combination of input voltage and output voltage management and regulation may be performed within the converter. The source voltage and current characteristic may be shaped to correspond to an optimized power curve at the desired bus voltage to allow MPPT tracking according to the DC voltage bus. The optimized power curve may be tracked to hold the DC-bus voltage at the desired operating point.

Constraint weighted regulation of DC/DC converters

A converter unit configured to couple to a photovoltaic panel (PV) may include a controller to sense an output voltage and output current produced by the photovoltaic panel, and manage the output voltage of a corresponding power converter coupled to a DC bus to regulate the resultant bus voltage to a point that reduces overall system losses, and removes non-idealities when the panels are series connected. The controller may also adapt to output condition constraints, and perform a combination of input voltage and output voltage management and regulation, including maximum power point tracking (MPPT) for the PV. The output voltage and output current characteristic of the power converter may be shaped to present a power gradient&#x2014;which may be hysteretically controlled&#x2014;to the DC bus to compel an inverter coupled to the DC bus to perform its own MPPT to hold the DC-bus voltage within a determinate desired operating range.

Regulation of inverter DC input voltage in photovoltaic arrays

A converter unit to improve the response dynamics and overall recovered power in a photovoltaic array configuration. Each photovoltaic panel in the photovoltaic array may be coupled to a respective converter unit, which may include a controller to sense an output voltage and output current produced by the solar panel, and control operation of a power converter to output modified voltage and current corresponding to the solar panel onto a bus coupling the converter units. The controller may operate as an analog or (digital) firmware control system to regulate the input voltage of each power converter unit under indirect guidance of a Maximum Power Point Tracking (MPPT) controller to optimize and regulate the resultant power, and achieve very fast dynamic response to environmental transients. Input voltage and output voltage management may be achieved by way of a fast inner control loop and a corresponding MPPT control system configured as an outer guidance loop providing a reference signal to the inner control loop.

Dual-loop dynamic fast-tracking MPPT control method, device, and system

A converter unit configured to couple to a photovoltaic panel (PV) may include a controller to sense an input voltage and input current obtained from the photovoltaic panel, and manage the output voltage of a corresponding power converter coupled to a DC bus to regulate the resultant bus voltage to a point that reduces overall system losses, and removes non-idealities when the panels are series connected. The controller may also perform input voltage management and regulation, including maximum power point tracking (MPPT) for the PV. The controller may probe the bus voltage using a probe waveform generated according to a pseudo-random bit sequence (PRBS), to provide a probe signal that is distinct from the control steps performed by the controller. A PV array may feature a respective converter unit coupled to each PV, with each respective controller using a different and unique seed for generating its PRBS.

Pseudo-random bit sequence generation for maximum power point tracking in photovoltaic arrays

A converter unit configured to couple to a photovoltaic panel may include a controller that monitors: an output voltage and output current obtained from the photovoltaic panel by a switching power core within the converter unit, and an output voltage and output current produced by the switching power core. The controller may calculate a desired duty-cycle value based on the monitored values, and implement a mapping algorithm that translates the duty-cycle value to a pulse-width value and a modulus value. The pulse-width value and the modulus value may be used to simultaneously respectively modulate the pulse-width and pulse-period of a pulse-width modulated (PWM) signal, while maintaining an appropriate linear final duty-cycle ratio between the pulse-width and the pulse-period of the PWM signal. The PWM signal may be provided to the switching power core to control the switching of the switching power core.

Dynamic frequency and pulse-width modulation of dual-mode switching power controllers in photovoltaic arrays

A solar power array includes solar power panels, where each solar panel provides output current and voltage, separate DC-DC converters, where each solar panel is connected to a unique DC-DC converter, where each DC-DC converter is designed to maximize the power from each solar panel, and where each DC-DC converter produces a high voltage output, a high voltage DC bus coupled to the DC-DC converters that receives the high voltage output, and a DC-AC inverter that inverts the high voltage DC on the high voltage DC bus to an AC power signal for distribution to one or more AC loads.

Solar power array with maximized panel power extraction

A method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal and a position of the first edge, (B) determining if the position is within a zone, (C) if the edge is not within the zone, adjusting the clock signal towards the position of the edge, (D) detecting a second edge of the data signal and a position of the second edge, (E) determining a in value indicating a position of the second edge, (F) adding the first value to a second value, wherein the second value indicates a position of a third edge of the data signal and (G) adjusting the clock signal based on the result of step (F).

Linearized digital phase-locked loop

A method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal, (B) determining a first value indicating a position of the first edge, (C) adding the first value to a second value, wherein the second value indicates a position of a second edge of the data signal and (D) adjusting the clock signal, based on the result of step (C), if the result is greater than a predetermined value.

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) a first reference signal in response to a pump-up signal and (ii) a second reference signal in response to a pump-down signal. The second circuit may be configured to generate (a) a first control signal in response to (i) the pump-up signal and (ii) the second reference signal and (b) a second control signal in response to (i) the pump-down signal and (ii) the first reference signal.

Frequency acquisition rate control in phase lock loop circuits

A deserializer within, for example, a transceiver is provided having multiple stages of pipelined demultiplexers. Each demultiplexer within the earlier stages of the pipelined architecture use only three latches. Two latches are dedicated to producing an odd bitstream (or even bitstream) from odd and even bits within the incoming serial bitstream. Another latch is dedicated to producing an even bitstream (or odd bitstream) from even and odd bits of the serial bitstream. Using only three latches within early stages of the pipelined architecture reduces power consumption and overall size of the deserializer. Clocking signal frequencies of subsequent stages are reduced and the clocking signals are delayed in order to align data outputs from the previous stage with transitions of clocking signals forwarded to the respective stages.

Low power deserializer circuit and method of using same

A method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal, (B) determining a first value indicating a position of the first edge, (C) adding the first value to a second value, wherein the second value indicates a position of a second edge of the data signal and (D) adjusting the clock signal based on the result of step (C).

Linearized digital phase-locked loop method

An apparatus for determining a state of a plurality of clock signals, comprising a circuit configured to store a state of each of said plurality of clock signals upon an edge of a data signal.

A circuit and method comprising a charge pump having a first and a second differential element. The charge pump may be configured to generate a first and a second output signal in response to the first and second differential elements. The first differential element may comprise (i) a first unity gain buffer and (ii) a first and a second transistor pair configured to receive a first and second control signal. The second differential element may comprise (i) a second unity gain buffer and (ii) a third and a fourth transistor pair configured to receive the first and second control signals. The first and second unity gain buffers may stabilize the source nodes of each of the transistors pairs.

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Austin, TX, United States of America

Bertrand Jeffery Williams