International Business Machines Corporation

U.S. Philips Corporation

Globalfoundries Inc.

Bertrand Gabillard

Philippe Girard

Michel Rivier

Francis Bredin

Philippe Hauviller

Thierry Ducourant

Jean-Noel Patillon

Alexandre Maltere

Fabrice Voisin

John J Ellis-Monaghan

Martin Aureliano Hassner

Barry Marshall Trager

Manfred Ernst Schabes

Patrice Gamand

Francesco Brianti

Dominique M Omet

Gerard M Martin

Christopher Ro

Michel J Grandguillot

Marc Rocchi

Yoshiaki Sonobe

Phillippe Hauviller

Michel Granguillot

Francois Auguste Roger Meunier

Checking the layout integrity includes the steps of receiving inputs defining a plurality of devices for a layout, generating a signature for each device in the layout, when created, from one or more parameters of the device, storing the generated signatures with the layout, receiving the stored layout and signatures, regenerating each signature for each device in the stored layout, and comparing each regenerated signature with the corresponding stored signature.

Method of checking the layout integrity

A circuit for providing a bandgap voltage. The circuit includes a classic bandgap reference voltage generation circuit including first end second serially connected transistors acting as a current mirror to another portion of the classical bandgap reference circuit and being coupled between a supply voltage Vand an output resistor. The circuit also includes a current trimming circuit coupled in parallel with the classical bandgap reference generation circuit including a fixed element portion including a plurality of transistors and a switch portion including a plurality of switches. Each of the plurality of transistors is coupled to the supply voltage Vand to a one of the plurality of switches and each switch includes a fuse.

Bandgap reference generator utilizing a current trimming circuit

There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second stage of one comparator. By properly activating the switches with signals generated by a dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation.

Receiver having full signal path differential offset cancellation capabilities

A differential sampling circuit is configured around a differential operational amplifier and is provided with a pair of switched-capacitor networks, each including an circuit block, to generate the real value of the differential input signal DC offset at each system clock cycle. During the first half cycle, the differential input signal pair (Vin+,Vin&#x2212;) is sampled and the holding capacitors in each network are charged. During the second half cycle, the differential input signal pair is sampled again and the holding capacitors are further charged. At the end of the cycle, the charges held in the holding capacitors are applied to the differential operational amplifier, so that the differential output signal is equal to the real differential input signal DC offset value.

Differential sampling circuit for generating a differential input signal DC offset

There is disclosed an improved differential amplifier () having a feedback loop that generates an amplified output signal (Vout) from an input signal (Vin) supplied by a preceding stage. It comprises an input matching circuit () connected to said preceding stage, a buffer () and an amplification section () connected in series in the direct amplification line, a first amplifier (), a RC network (') and a second amplifier () connected in series in a parallel loop between the outputs and the inputs of the amplification section that generate the feedback signal. The role of said buffer and second amplifier associated in a dedicated direct and feedback signal combining block () is to respectively isolate the input signal and the feedback signal from the summing nodes (A&#x2032;,B&#x2032;) at the amplification section inputs. As a result, the summation of the input signal and the feedback signal is improved, the DC component of the output signal is filtered out in order to significantly reduce the DC offset. In addition, the input impedance matching represented by parameter Sis considerably improved.

Differential amplifier with DC offset cancellation

There is disclosed an improved 2-stage large bandwidth amplifier () comprised of two stages formed by first and second bipolar transistors (Q,Q) configured in common emitter that are connected in series with their emitters connected to a first supply voltage (Gnd). The input signal (V) is applied to the base of said first transistor via an input terminal (), while the output signal (V) is available at an output terminal () connected to the collector of said second transistor. A parallel feedback structure (') is provided. It consists, in a first branch, of two diodes (D,D) in series connected between a second supply voltage (Vcc) and the collector of the second bipolar transistor, and in another branch of a third bipolar transistor (Q) configured in emitter follower with a resistor (Rf) in the emitter. The base and the collector of said third bipolar transistor are respectively connected to the common node of said diodes and to said second supply voltage. The resistor is connected to the common node of said first and second transistors to inject the feedback signal (V). Because, the two bodies have a low internal resistance and reduce the collector capacitance of the second transistor, the overall bandwidth of the improved amplifier is significantly extended in the very high frequencies (e.g. 20 GHz and above).

2-stage large bandwidth amplifier using diodes in the parallel feedback structure

An improved voltage to current converter circuit having three stages. The first stage amplifies the input voltage signals. The second stage includes first and second/third current sources that are connected in a current mirror configuration with a common node therebetween. The third stage consists of an output transistor to form a half cascode current mirror having its drain connected to the second/third current sources and to the output terminal. The gate of the output transistor is coupled to a bias voltage and to the drain of an additional transistor so that the potential on the gate of the output transistor can vary to have both transistors of the third stage in the saturation state for a wide range of the current flowing through the transistors of the half cascode current mirror.

Voltage to current converter circuit

A non-integer fractional divider is disclosed. According to the present invention, the non-integer fractional divider comprises means for dividing a reference clock signal having a period 'P' by a non-integer ratio 'K'. In a preferred embodiment, the divider comprises means for receiving a plurality &lsquo;N&rsquo; of clock signals issued from the reference clock signal and wherein each clock signal is equally phase shifted by a &lsquo;P/N&rsquo; delay one over the other. Selection means are coupled to the receiving means for selecting a first and a second clock signals between the plurality &lsquo;N&rsquo; of clock signals. The selected clock signals are such that the phase shift delay between the two selected clock signals is representative of the non-integer value of the ratio &lsquo;K&rsquo;. The selected clock signals are combined into combining means to generate a clock signal being phase shifted by the non-integer part of the non-integer ratio. Then, dividing means are coupled to the combining means for dividing the shifted clock signal by the integer part of the non-integer ratio.

Programmable non-integer fractional divider

A non-integer fractional divider divides a reference clock signal having period P by a non-integer ratio K. The divider includes multiplexers to receive a plurality N of clock signals wherein each clock signal is equally phase shifted by a P/N delay. Incrementers coupled to the multiplexers select first and second clock signals between the N clock signals. Such that the phase shift delay between the two selected clock signals is representative of the non-integer value of K. The selected clock signals are combined to output a divided clock signal. The enabling time of each selected clock signal is respectively representative of the duration of the low level and the high level of the divided clock signal.

A Hilbert transform is used to process perpendicular magnetic recording signals from both single layer and dual layer disks to produce a complex analytic signal. This complex analytic signal is used to derive angles of magnetization, which depend on the distance between recorded magnetic transitions and consequently which can be used in error estimation. Moreover, the Hilbert transform in cooperation with an equalizer FIR optimizes transformation of the signal such that conventional longitudinal recording processing methods can subsequently be used to process the signal that is read back from the magnetic recording medium.

Perpendicular signal equalization and timing recovery using Hilbert transform

A test circuit applicable to chips having embedded arrays intermixed with logic is described. Depending on a control signal, the test circuit connects or isolates the arrays to and from the logic. The test circuit operates as a switch placed between the power supply rail of the logic and the power supply rail of the arrays. All input gates are cross-connected to the power supply rail of the logic, and each output gate is connected to the corresponding power supply rail of the arrays. During TEST mode, the control signal turns off the test circuit, cutting off the arrays. The logic is tested while the memory cells remain unselected. Faulty chips are rejected. When the value of the control signal is inverted, a control gate connects all the power supply rails of the arrays to the power supply rail of the logic. The test sequence for the embedded array is then applied. Faulty memory cells are replaced with repairable ones; otherwise, the faulty chips are rejected. Thus, the manufacturing yield of the mixed chips is improved.

Circuit for testing a semiconductor chip having embedded arrays

A cache memory architecture having a separate redundant read bus fully dedicated to redundancy and fed by a single spare sub-array common to all memory sub-arrays of the cache memory. Redundant sense amplifiers are dotted to the redundant read bus, and normal sense amplifiers are connected to a main read bus. Normal and redundant data are valid and available at the same time at the outputs of the normal and redundant sense amplifiers. When the late select address signals become valid, then the correct information can be selected via a multiplexer provided with an INHIBIT input. The multiplexer is normally controlled by decoded signals generated by a decoder, unless redundancy is required. If redundancy is required, the information generated by the bit address comparator forces the multiplexer, via the INHIBIT input, to select the redundant read bus, instead of one read bus of the main read bus, and to output the redundant byte as the selected one.

Redundant read bus for correcting defective columns in a cache memory

A plurality of local address transition detector (LATD) circuits, one per address bit signal (Ai), of the type used in SRAMs to generate an on-chip clock pulse (LATDSi) that insures a correct timing of internal circuits such as sense amplifiers and address decoders that are essential for a correct READ/WRITE operation of the SRAM. According to one aspect of the invention, each LATD circuit includes: a first bipolar transistor (T1) serially connected with a first FET device (N1) forming a first branch; a second bipolar transistor (T2) serially connected with a second FET device (N2) forming a second branch. The first and second branches are connected in parallel between a first supply voltage (Vcc) and a common output node (N) connected to a circuit output terminal (30-i) where the output signal (LATDSi) generated by the LATD circuit (22-i) is available. The first and second bipolar transistors (T1, T2) are respectively driven by the address signal (Ai') and its complement (Ai') at the ECL voltage levels and the second and first FET devices are respectively driven by the address signal (Ai*' ) and its complement (Ai*') at the CMOS voltage levels. As a result of this design of the LATD circuit, the delays in critical paths in BICMOS circuits incorporating the LATD circuit may be significantly reduced relative to BICMOS circuits utilizing conventional LATD circuits.

BICMOS local address transition detection circuit

Input ECL level signals are received and converted into output CMOS level signals by input buffer (30). The input buffer (30) biased between first and second supply voltage (Vcc, Vee) and is comprised of three stages. The first stage (11A) consists of a conventional emitter-follower transistor (Q1) and a current-switch (13) connected in series. The input signal VIN at the ECL level is applied to the base of the emitter-follower transistor (Q1). The output signals (VA, VB) obtained therefrom drive a second stage which consists of an input buffer circuit (20), which supplies two pairs of output signals (V1) V2; V1', V2') for each phase. Each pair of output signals drives an output driver (31; 31') forming the third stage. The input buffer circuit (20) is composed of two NPN bipolar transistor (T1; T2) connected in an emitter-follower configuration forming two branches. In each branch, the emitter load consists of three FET devices: two PFETs (P1, P3; P2, P4 ) and one NFET (N1; N2) serially connected. The common node (E; F) between the PFETs in one branch, is cross-coupled to the gate electrode of the NFET (N2; N1) of the other branch. The gate electrode of the PFET (P1; P2) connected to the emitter of the bipolar transistor (T1; T2) in one branch is driven by the potential of the common node formed by the other PFET (P4, P3) and the NFET (N2; N1) in the other branch. The IN PHASE (VOUT) and OUT OF PHASE (VOUT) circuit output signals are available at the circuit output terminals (32; 32') of said output drivers (31; 31') at the CMOS levels.

Level-shifter circuit for high-speed low-power BiCMOS ECL to CMOS input

An integrated semiconductor device including a frequency divide-by-two circuit comprising an inverter stage and a switching transistor (T2) which is controlled by a microwave input signal (E). The divider circuit includes an oscillator stage in that the inverter stage is at least equipped with a reactive element which in combination with the inverter stage forms a negative resistant network. The switching transistor is connected in parallel with this reactive element and the transmit time .tau..sub.0 of the switch is less than the transit time .tau..sub.2 of a signal propagating through the reactive element.

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Paris, France

Bertrand Gabillard