Siemens Aktiengesellschaft

International Business Machines Corporation

Infineon Technologies North America Corp.

Bertrand Flietner

K Paul Muller

Herbert Lei Ho

Gary Bela Bronner

Rajiv M Ranade

Alexander Michaelis

Erwin Hammerl

Radhika Srinivasan

Robert Ploessl

Wolfgang Bergner

Farid Agahi

Klaus Roithner

Monika Gschoederer

A method of forming a buried plate in a silicon substrate uses a silicon substrate having a deep trench etched into the silicon substrate. A highly doped polysilicon layer is formed within the trench. A nitride layer is then formed within the trench over the polysilicon layer. After forming both the polysilicon layer and the nitride layer, both the polysilicon layer and the nitride layer are etched from a certain uppermost portion of the sidewalls of the trench thereby exposing the silicon substrate at the uppermost portions of the sidewalls. After exposing the silicon substrate at the uppermost portions of the sidewalls, a collar oxide layer is formed over the exposed silicon substrate at the uppermost portions of the sidewalls thereby protecting any edges of the polysilicon layer exposed by the etching step.

Self aligned buried plate

A gas distribution plate ( ) for a semiconductor processing chamber ( ) includes a gas distribution plate for distributing gases across a surface of a semiconductor wafer ( ) to be processed in the chamber. The gas distribution plates has a substantially planar member having gas outlets for distributing a reactant gas across the surface of the semiconductor wafer, the gas outlet means includes a plurality of apertures ( ) defined in said planar member, the plurality of apertures having different areas at predetermined locations to adjust etching gas flow. A pump ( ) is provided for evacuating a reactant-product gas created across the surface of the semiconductor wafer during wafer processing. The pump ( ) includes a plurality of tubes extending through the planar member, the plurality of tubes having apertures, and the apertures have different areas at predetermined locations to adjust reactant gas and reactant-product gas flow wherein the gas outlets and the pump coact to substantially maintain a predetermined concentration of the reactant gas and a predetermined concentration of the reactant-product gas across the surface of the semiconductor wafer during wafer processing.

Spatially uniform gas supply and pump configuration for large wafer diameters

A measurement device for in-situ measurement of processing parameters, in accordance with the present invention, includes a semiconductor wafer having at least one processed chip formed thereon. The processed chip further includes at least one sensor for measuring process parameters. A memory storage device for storing the process parameters as the process parameters are measured by the at least one sensor is also included. A timing device is provided for tracking the process parameters as a function of time, and a power supply is included for providing power to the at least one sensor, the memory storage device and the timing device. Also, a method is described for making measurements with the measurement device.

In-situ measurement method and apparatus for semiconductor processing

A reduction in parasitic leakages of shallow trench isolation vias is disclosed wherein the distance between the silicon nitride liner and the active silicon sidewalls is increased by depositing an insulating oxide layer prior to deposition of the silicon nitride liner. Preferably, the insulating oxide layer comprises tetraethylorthosilicate. The method comprises of etching one or more shallow trench isolations into a semiconductor wafer; depositing an insulating oxide layer into the trench; growing a thermal oxide in the trench; and depositing a silicon nitride liner in the trench. The thermal oxide may be grown prior to or after deposition of the insulating oxide layer.

Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI

An improved hard mask is provided to reduced pad erosion during semiconductor fabrication. The hard mask includes an etch stop layer between first and second hard mask layers.

Reduced pad erosion

A vertical trench in a silicon wafer for use in forming the storage capacitor of a DRAM is etched by reactive ion etching in a manner to have a profile that has multiple waists. This profile is obtained by varying the rate of flow of coolant in the base member on which the silicon wafer is supported during the reactive ion etching to vary the temperature of the silicon wafer during the etching. Alternatively, the multiple waists are achieved by either by varying the ratio of the different gases in the etching chamber or the total gas pressure in the chamber.

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Hopewell Junction, NY, United States of America

Bertrand Flietner