Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Aledia

Centre National De La Recherche Scientifique

Université´ D'aix-Marseille

Bertrand Chambion

Jean-Philippe Colonna

Stéphane Caplet

Adrien Gasse

Stephan Borel

David Henry

Vincent Beix

Brigitte Soulier

Emmanuel Hugot

Abdenacer Ait-Mani

Thomas Lacave

Fabienne Goutaudier

Romain Soulas

A process includes providing electronic chips, the chips having been diced beforehand and each including a stack including a matrix-array of pixels, an interconnect layer, first layer, joining the electronic chips to a carrier substrate, so as to leave a spacing region between the chips; forming a redistribution layer having lateral ends extending into each spacing region; forming metal pillars on the lateral ends; moulding a material including first segments, facing the first layers, second segments which are separate from the first segments, and which extend around the metal pillars; the first and second segments being coplanar; applying a heat treatment, the formed material being chosen so that the stack is curved with a convex shape; the second segments remaining coplanar at the end.

Process for collectively curving a set of electronic chips

A wafer-level process includes providing a set of electronic chips, including a stack with a set of matrix arrays of pixels, an interconnect layer electrically connected to the set of matrix arrays of pixels, and a first layer, including vias electrically connected to the interconnect layer. The wafer-level process further includes forming metal pillars on the first layer, the pillars being electrically connected to the vias, and forming a material integrally with the first layer, around the metal pillars. The wafer-level process also includes dicing the electronic chips so as to release the thermomechanical stresses to which the stack is subjected. Finally, the wafer-level process includes making the metal pillars coplanar after dicing the electronic chips.

Wafer-level process for curving a set of electronic chips

A method of manufacturing a device includes: &#x2014;a) a first step for the formation of a temporary structure that comprises electroluminescent structures separated by trenches and comprising an electroluminescent face, the electroluminescent structures being bonded by means of a bond layer on a temporary substrate; b) an assembly step bringing the electroluminescent structures into contact with a host face of a host substrate; and c) a step for removal of the temporary substrate; wherein the bond layer, that comprises an electrically conducting organic polymer material at least partially transparent to light radiation, is at least partly kept after step c) and forms an electrode common to the light emitting faces, with a thickness of more than 20 nm.

Method for manufacturing an electroluminescent device

The invention relates to a method for producing a first microelectronic chip including a layer of interest having a connection face, intended to be hybridized with a second microelectronic chip. The method including depositing a layer of adhesive on a face of the layer of interest opposite to the first connection face and fastening a handle layer to the layer of adhesive. The method also includes, prior to the steps of depositing the adhesive and fastening the handle layer, defining, on the one hand, a maximum thickness eand a minimum value Eand a maximum value Eof the Young's modulus for the layer of adhesive, and, on the other hand, the minimum thickness efor the handle layer.

Method for producing a microelectronic chip to be hybridised to a second chip

A method for producing curved electronic circuits is provided, including placing adhesive elements between electronic chips and curved bearing surfaces, with the chips disposed between the surfaces and a flexible film, and such that the chips, the elements, and the surfaces are arranged in a single volume to be depressurised towards an environment outside the volume, the volume including empty spaces between the chips and the surfaces, the spaces being in fluid communication with each other within the volume; establishing a pressure difference between an inside and an outside of the volume such that the film applies a pressure on and collectively deforms the chips in accordance with the surfaces; and stopping the establishing of the pressure difference, the chips being collectively maintained against the surfaces by the elements such that a shape of each of the chips conforms to a corresponding shape of each of the surfaces.

Method for producing curved electronic circuits

An electronic circuit including: an electronic component, a conductive armature surrounding the electronic component, an electrical insulator between the electronic component and the conductive armature, a device configured to measure current passing through the armature or voltage on the armature or on the electronic component, and a defect determination device configured to determine a defect in the electrical insulator based on the measured current or voltage.

Integrated circuit intended for insulation defect detection and having a conductive armature

An electronic structure includes a plurality of electronic devices arranged in the form of a matrix array including a first number of rows, the electronic devices of each row being connected in series, the matrix array further including a plurality of switches, the rows of the matrix array being distributed in a second number of groups intended to be connected in series by the switches, the groups connected in series being supplied with an electrical supply current, at least one of the groups including at least two rows connected in parallel so as to distribute the supply current between the at least two rows.

Electronic structure comprising a matrix array of electronic devices having improved thermal performances

A method for producing a plurality of curved electronic circuits includes: producing a support including a plurality of membranes made from at least one material having a rigidity of more than around 100 MPa, each intended for being part of one of the electronic circuits and having a radius of curvature R between about 15 mm and 500 mm; applying a force to one of the main surfaces of each of the membranes, so that the membrane deforms resiliently and has a substantially planar shape when exposed to the force; rigidly connecting at least one electronic component to each of the membranes; and removing the force applied to one of the main faces of each of the membranes so that each of the membranes retrieves its original radius of curvature R and curves the electronic component according to this radius of curvature R.

Method for mass-production of curved electronic circuits

An electronic circuit including a semiconducting or conducting substrate having first and second opposite surfaces and at least first and second non-parallel electrically insulating trenches that extend from the first surface in the substrate, define at least one portion of the substrate and join at a junction, the portion of the substrate including a protrusion that extends to the junction.

Electronic circuit comprising electrically insulating trenches

This method comprises the steps of: a) forming a set of first trenches on the first surface of the wafer; b) forming a set of second trenches on the second surface of the wafer, at least partially facing the first trenches; c) filling the first trenches with a first material having a CTE &#x3b1;; d) filling the second trenches with a second material having a CTE &#x3b1;, and verifying &#x3b1;&#x3e;&#x3b1;or &#x3b1;&#x3c;&#x3b1;depending on whether the first material verifies &#x3b1;&#x3e;&#x3b1;or &#x3b1;&#x3c;&#x3b1;.

Growing community of inventors

Pontcharra, France

Bertrand Chambion