Qimonda Ag

Bernhard Ruf

Thomas Happ

Petra Majewski

Dieter Andres

Jan Boris Philipp

Christian Rüster

Franz Kreupl

Ulrich Karl Klostermann

Michael Kund

Klaus-Dieter Ufert

Ulrike Gruening-von Schwerin

Ralf Symanczyk

Michael Angerbauer

Rainer Bruchhaus

Christian Ruester

According to an embodiment, an integrated circuit including a plurality of resistance changing memory cells is disclosed. Each memory cell includes a first electrode, a second electrode and resistance changing memory element arranged between the first electrode and the second electrode. A front surface area of an end section of the first electrode that faces the resistance changing memory element is smaller than a front surface area of an end section of the second electrode that faces the resistance changing memory element.

Integrated circuit

A method for fabricating an integrated circuit, the method comprises forming a first electrode, depositing resistance changing material over the first electrode, the resistance changing material having an active zone for switching the resistance of the resistance changing material and an inactive zone, and forming a second electrode over the resistance changing material. The chemical composition of the resistance changing material in the active zone differs from the chemical composition of the resistance changing material in the inactive zone.

Method for fabricating an integrated circuit including memory element with spatially stable material

An integrated circuit includes a heater element serving as a first electrode, a second electrode, a memory element comprising resistance changing material coupled to the heater element and to the second electrode, and a diffusion compensation region coupled to the heater element and to the resistance changing material. The diffusion compensation region includes a surplus of at least one diffusible species present in the memory element and provides at least one diffusible species to the memory element.

Integrated circuit including memory element with spatially stable material

An integrated circuit includes a resistance changing memory element and a circuit. The circuit is configured to program the memory element to a crystalline state from an amorphous state by applying a seed pulse to the memory element followed by a set pulse.

Integrated circuit including a memory element programmed using a seed pulse

A device and method are disclosed for electrical contacting of semiconductor devices for testing. One embodiment provides for testing semiconductor devices or integrated circuits, including a probe card with contact tips for the electrical contacting of the semiconductor devices. The electrical connection of at least one contact tip to the test system is adapted to be switched via a resistively switching memory cell. A resistively switching memory cell in the form of a nano switch is integrated in the electrical connection of the contact tip.

Device and method for electrical contacting semiconductor devices for testing

An integrated circuit includes an array of resistance changing memory cells and a first circuit. The first circuit is configured to set a selected memory cell to a crystalline state by applying a decreasing stair step pulse to the selected memory cell. The pulse is based on a reset current distribution for the array of memory cells.

Integrated circuit for setting a memory cell based on a reset current distribution

A memory device and a method of operating a memory device is disclosed. In one embodiment of the invention, the memory device includes a plurality of multi-level memory cells each having a number m of levels not matching 2with n being a non-zero integer, and a circuit or device for combining the levels of at least two of the memory cells for write and read operations into a set of combined states and for transforming at least a subset of 2combinations of the set of combined states into n two-level data bits.

Growing community of inventors

Sauerlach, Germany

Bernhard Ruf