International Business Machines Corporation

Infineon Technologies Ag

Mentor Graphics Corporation

Bernhard R Liegl

Timothy A Brunner

Stephen Edward Greco

Hua Xiang

Enio L Carpi

Lawrence Alfred Clevenger

Steven J Holmes

Kevin Shawn Petrarca

Wai-Kin Li

Wu-Song S Huang

Laertis Economikos

Kafai Lai

Sean David Burns

Roger Allan Quon

Kuang-Jung Chen

Colin J Brodsky

Scott Josef Bukofsky

Choongyeun Cho

Brian Christopher Sapp

Peter Thwaite

Xiaochun Linda Chen

Lawrence Varnerin

A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

System and method of predicting problematic areas for lithography in a circuit design

A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.

Method and system to predict lithography focus error using simulated or measured topography

An anti-reflective coating material, a microelectronic structure that includes an anti-reflective coating layer formed from the anti-reflective coating material and a related method for exposing a resist layer located over a substrate while using the anti-reflective coating layer provide for attenuation of secondary reflected vertical alignment beam radiation when aligning the substrate including the resist layer located thereover. Such enhanced vertical alignment provides for improved dimensional integrity of a patterned resist layer formed from the resist layer, as well as additional target layers that may be fabricated while using the resist layer as a mask.

Photolithography focus improvement by reduction of autofocus radiation transmission into substrate

The invention relates to a method for determining processing image induced defects in the manufacture of semiconductor products such as wafers by analyzing the circuit design of the product mask and modifying a conventional test defect structure to mimic the product mask to incorporate one or more isolated or other features including product mask circuit features likely to cause processing image induced defects into the test defect structure.

Proximity sensitive defect monitor

A method and apparatus are provided for improving the leveling and, consequently, the focusing of a substrate such as a wafer during the photolithography imaging procedure of a semiconductor manufacturing process. The invention performs a pre-scan of the wafer's topography and assigns importance values to different regions of the wafer surface. Exposure focus instructions are calculated based on the topography and importance values of the different regions and the wafer is then scanned and imaged based on the calculated exposure focus instructions.

Density-aware dynamic leveling in scanning exposure systems

Corner rounding and image shortening is substantially reduced in an image printed on a substrate by illuminating a photolithographic mask and projecting light transmitted through the photolithographic mask onto the substrate using an optical projection system. The photolithographic mask has a mask pattern that includes at least one printable feature having at least one corner. Incorporated, in the mask pattern, is at least one line feature corresponding to the corner of the printable feature. The line feature is in at least close proximity to the corresponding corner of the printable feature and has a line width that is smaller than a minimum resolution of the optical projection system.

Sub-resolution sized assist features

There is provided a method for aligning a semiconductor wafer and a mask. A semiconductor wafer is provided having an alignment mark formed thereon. A mask is provided having a pattern formed thereon. The mask is illuminated so as to create a bright spot thereon by a 0_&pgr; phase conflict. The alignment mark is aligned with the bright spot, so as to align the semiconductor wafer with the mask. Preferably, the method includes the step of creating the alignment mark on the semiconductor wafer in a form of a frame. Moreover, preferably, the creating step includes the step of creating the frame to minimize an impact of film stack variations.

Alignment system and method using bright spot and box structure

A method for intra-cell alignment of a substrate and mask comprises providing a substrate comprising an exposed photosensitive material, providing a phase-shift mask, and aligning the phase-shift mask to an intra-cell structure on the substrate.

Intra-cell mask alignment for improved overlay

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Beacon, NY, United States of America

Bernhard R Liegl