Texas Instruments Corporation

Bernhard P Lange

Anthony Louis Coyle

Steven Alfred Kummerl

Quang X Mai

A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.

Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices

A high current semiconductor device (for example QFN for 30 to 70 A) with low resistance and low inductance is encapsulated by molding compound (, heightabout 0.9 mm) so that the second lead surfacesremain un-encapsulated. A copper heat slug () may be attached to chip surface () using thermally conductive adhesive (). Chip surface (), protected by an overcoat () has metallization traces (). Copper-filled windows () contact the traces and copper layers () parallel to traces (). Copper bumps () are formed on each line in an orderly and repetitive arrangement so that the bumps of one line are positioned about midway between the bumps of the neighboring lines. A substrate has elongated leads () oriented at right angles to the lines; the leads connect the corresponding bumps of alternating lines.

High current semiconductor device system having low resistance and inductance

A semiconductor device comprising a leadframe (), which has first () and second () surfaces, a planar pad () of a certain size, and a plurality of non-coplanar members () adjoining the pad. The device further has a heat spreader () with first () and second () surfaces, a planar pad of a size matching the leadframe pad size, and contours (), into which the leadframe members are inserted so that the first spreader pad surface touches the second leadframe pad surface across the pad size. A semiconductor chip () is mounted on the first leadframe pad surface. Encapsulation material (), preferably molding compound, covers the chip, but leaves the second spreader surface uncovered.

Semiconductor device having firmly secured heat spreader

A device () and method () for bonding a ribbon wire () to a workpiece () comprising feeding the ribbon wire through a passageway () of an ultrasonic bond capillary () and clamping the ribbon wire against an engagement surface () of the bond capillary via a clamping jaw () operably coupled to the bond capillary. The ribbon wire () is bonded to the workpiece () along a bonding surface () of the bond capillary () and penetrated, at least partially, between the bonding surface and the engagement surface () of the bond capillary by a cutting tool (). The cutting tool () may comprise an elongate member () positioned between the bonding surface () and engagement surface (), and may have a cutting blade () positioned at a distal end () thereof. The cutting tool () may further comprise a ring cutter (), wherein the ribbon wire passes through a ring () having a cutting surface () defined about an inner diameter thereof.

Bond capillary design for ribbon wire bonding

An integrated circuit chip packaging assembly having a first and second package side. An integrated circuit chip has a substrate side and an active circuit side. The chip includes integrated circuit devices formed on the active circuit side. The active circuit side of the chip is on the first package side. The die pad has at least one runner member extending therefrom, which may be bent toward the first package side. The active circuit side of the chip is attached to the die pad. The die pad is on the first package side relative to the chip. The package mold compound is formed over the die pad, at least part of the chip, and at least part of the runner member(s). At least part of the substrate side of the chip and/or at least part of the runner member(s) may not be covered by the package mold compound.

Integrated circuit chip packaging assembly

A device comprising a semiconductor chip () having a side edge () and a plurality of metal bond pads () near the edge; the pads are aligned to form rows () parallel to the edge. The device further includes a leadframe () having leads (. . . ) oriented with one end (. . . ) towards the chip edge and spaced from it by a gap (); the chip is attached to the leadframe. Ends of selected leads are connected by a metal cross bar () parallel to the chip edge. Substantially parallel bond wires () are crossing the gap to connect each chip pad either to the crossbar or to a non-selected lead end. In a preferred lead arrangement, the selected leads alternate with non-selected leads.

Semiconductor assembly and packaging for high current and low inductance

According to one embodiment of the invention, a method of die attach includes providing a chip, forming a heat conductive metal layer outwardly from a backside of the chip, and coupling the chip to a substrate. The heat conductive metal layer has a thickness of at least 0.5 mils.

System and method for die attach using a backside heat spreader

A semiconductor package comprising a die adjacent a lead frame die pad, said lead frame die pad adapted to dissipate heat from the die. The package further comprises a thermally-conductive material abutting the die and a heatsink abutting the thermally-conductive material, said heatsink facing a direction opposite from the lead frame die pad.

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Garland, TX, United States of America

Bernhard P Lange