International Business Machines Corporation

Bernhard Laubli

Roger Gregory Hathorn

Charles Scott Cardinell

Timothy J Van Patten

Steven Edward Klein

Stephen LaRoux Blinick

Miguel A Montoya

John R Flanagan

William Frank Micka

Patricia G Driever

Louis William Ricci

Catherine C Huang

Joseph C Elliott

Jacob Lee Sheppard

Paul J Brown

Kenneth R Lynch

Mark Steven Bayus

Igor Popov

Paul S Frazer

Key management for encrypted data. A node, such as a storage device, obtains a shared key to be used in cryptographic operations. The obtaining includes using an identifier of another node, such as a host of the computing environment, and a unique identifier of the shared key to obtain the shared key. The obtained shared key is then used in one or more cryptographic operations.

Storage device key management for encrypted host data

A driver of a host bus adapter of a storage controller performs hardware resets of buses and other logic to which an embedded port of the host bus adapter is connected, in a first period of quiescing of I/O operations in the embedded port. The driver transmits one or more commands to the embedded port to resume selected I/O operations in the embedded port. A reinitialization of the driver is performed during a second period of quiescing of I/O operations in the embedded port, prior to sending a command to allow normal I/O operations in the embedded port.

Programming interface operations in a driver in communication with a port for reinitialization of storage controller elements

An embedded port of a host bus adapter of a storage controller receives, from a driver of the host bus adapter, a first set of commands to quiesce I/O operations in the embedded port for a first period, wherein hardware resets of buses and other logic to which the embedded port is connected are performed in the first period of quiescing of I/O operations. One or more commands are received to resume selected I/O operations in the embedded port. A second set of commands is received to quiesce I/O operations for a second period. A command is received to allow normal I/O operations, subsequent to the driver being reinitialized during the second period of quiescing of I/O operations.

Programming interface operations in a port in communication with a driver for reinitialization of storage controller elements

Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.

Locking a cache line for write operations on a bus

Provided are a computer program product, system, and method for determining processor offsets to synchronize processor time values. A determination is made of a master processor offset from one of a plurality of time values of the master processor and a time value of one of the slave processors. A determination is made of slave processor offsets, wherein each slave processor offset is determined from the master processor offset, one of the time values of the master processor, and a time value of the slave processor. A current time value of the master processor is adjusted by the master processor offset. A current time value of each of the slave processors is adjusted by the slave processor offset for the slave processor whose time value is being adjusted.

Determining processor offsets to synchronize processor time values

An approach to detecting processor failure in a multi-processor environment is disclosed. The approach may include having each CPU in the system responsible for monitoring another CPU in the system. A CPUreads a timestampcreated by CPUwhich CPUis monitoring from a shared memory location. The CPUreads its own timestampand compares the two timestamps to calculate a delta value. If the delta value is above a threshold, the CPUdetermines that CPUhas failed and initiates error handling for the CPUs in the system. One CPU may be designated a master CPU, and be responsible for beginning the error handling process. In such embodiments, the CPUmay initiate error handling by notifying the master CPU that CPUhas failed. If CPUis the master CPU, the CPUmay take additional steps to initiate error handling, and may broadcast a non-critical interrupt to all CPUs, triggering error handling.

Inter-processor failure detection and recovery

An apparatus for configuring a port in a multi-port communication adapter includes a quiesce module quiescing communications at one or more first I/O ports of a multi-port communication adapter while allowing communications at one or more second I/O ports of the multi-port communication adapter. A path module removes one or more logical paths between the one or more first I/O ports and one or more remote adapters in anticipation of taking the one or more first I/O ports offline. The offline module takes offline the one or more first I/O ports. The update module updates a port resource of the one or more first I/O ports while allowing a concurrent communication on the one or more second I/O ports of the multi-port communication adapter.

Adapter port configuration

A method, program product and apparatus for checkpointing for recovery of channels in a data processing system using a protocol which allows for multiplexing operations at the frame level and streaming of commands and data. For unsuccessful retries, the correct primary CCW address is reported back to software indicating the extent to which the channel completed modifying and accessing S/390 storage.

Checkpointing for recovery of channels in a data processing system

A mechanism for controlling the powering-on and powering-off of control units in a data processing system having a plurality of channels, a plurality of control units, and a communications network of links for linking the channels to the control units. Each control unit includes a power-control table for recording power-control allegiance of the control unit to the channels. Where a control unit receives a power-on command from a channel, it records the identity of the channel in its power-control table. When a channel orders a control unit to power-off, the control unit checks to see if it owes power-control allegiance to the ordering channel. If it does, the control unit deletes the identity from its power-control table. The control unit will not power-off unless its power-control table is empty, indicating that it does not owe allegiance to any other channel.

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Tucson, AZ, United States of America

Bernhard Laubli