Agere Systems Inc.

Bernhard Laschinsky

Neil Puthuff

Francis H Reiff

Million Woldesenbet

An integrated circuit (IC) having a link layer that (1) simultaneously receives both hardware debug data from on-chip ASIC logic and software debug data from an on-chip programmable processor and (2) serializes the hardware and software debug data streams to generate one or more serialized debug data streams, e.g., containing both hardware and software debug data, for output to off-chip debug testing equipment to support debug testing of both the ASIC logic and the programmable processor. Cross triggering can be implemented on-chip to support simultaneous display of correlated hardware and software debug information on appropriate monitors. The present invention supports debug testing using external debug testing equipment that does not require a hardware logic analyzer.

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Allentown, PA, United States of America

Bernhard Laschinsky