Infineon Technologies Ag

Infineon Technologies Austria Ag

Infineon Technologies Americas Corp.

Technische Universitaet Graz

Bernhard Goller

Francisco Javier Santos Rodriguez

Katharina Schmut

Hans-Joachim Schulze

Iris Moder

Michael Sorger

Magdalena Forster

Ingo Muri

Roland Rupp

Martin Poelzl

Ravi Keshav Joshi

Maximilian Roesch

Alexander Breymesser

Robert Paul Haase

Sylvain Leomant

Kamil Karlovsky

Philemon Schweizer

Andreas Peter Meiser

Rainer Leuschner

Thomas Feil

Tobias Franz Wolfgang Hoechbauer

Michael Sternad

Alexander Binter

Dirk Hammerschmidt

Vijaye Rajaraman

Guenter Zieger

Oliver Blank

Stephan Voss

Gerald Holweg

Helmut Oefner

Matthias Kuenle

Thomas Herndl

Karl Mayer

Peter Zorn

Matteo Piccin

Rafael Janski

Sophia Friedler

Christian Grindling

Horst Theuss

Mario Motz

Edward Fuergut

Manfred Engelhardt

Wolfgang Scherr

Hermann Wendt

Werner Schustereder

Carsten Von Koblinski

Wolfgang Lehnert

Jan Richter

Andre Brockmeier

Michael Roesner

Carsten Schaeffer

Gudrun Stranzl

Marko Swoboda

Gerald Lackner

Thomas Christian Neidhart

Ralf Rieske

Ronny Kern

Martin Zgaga

Joachim Hirschler

Guenter Denifl

Walter Leitgeb

Kurt Matoy

Sokratis Sgouridis

Markus Ottowitz

Petra Fischer

Mihai Draghici

Martin Huber

Guenter Schagerl

Eva-Maria Hess

Tobias Hoechbauer

Thomas Walter

Bernhard Boche

Guenther Wellenzohn

Wolfgang Diewald

Daniel Brunner

Daniel Pieber

Lukas Ferlan

Heimo Graf

Monika Cornelia Voerckel

Christian Schweiger

Bernd Noehammer

Christine Moser

Markus Bergmeister

Denis Lenardic

A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

Semiconductor device with a porous portion, wafer composite and method of manufacturing a semiconductor device

pa The method of processing a semiconductor wafer includes forming one or more epitaxial layers over its first main surface. It also involves forming one or more porous layers within the semiconductor wafer or within the epitaxial layers. Together, the semiconductor wafer, the epitaxial layer(s), and the porous layer(s) form a substrate. Next, doped regions of a semiconductor device are formed within the epitaxial layer(s). After forming these doped regions, a non-porous part of the semiconductor wafer is separated from the rest of the substrate along the porous layer(s).

Manufacturing and reuse of semiconductor substrates

A method of forming a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate; increasing the porosity of the first semiconductor layer; first annealing the first semiconductor layer in an atmosphere including an inert gas; forming a second semiconductor layer on the first semiconductor layer; and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer. Additional methods of forming a semiconductor device are described.

Methods for forming a semiconductor device having a second semiconductor layer on a first semiconductor layer

A method for producing MEMS components comprises generating a carrier having a plurality of recesses. An adhesive structure is arranged on the carrier and in the recesses. A semiconductor wafer is generated, which has a plurality of MEMS structures arranged at the first main surface of the semiconductor wafer. The adhesive structure is attached to the first main surface of the semiconductor wafer, with the recesses being arranged above the MEMS structures and the adhesive structure not contacting the MEMS structures. The semiconductor wafer is singulated into a plurality of MEMS components by applying a mechanical dicing process.

Method with mechanical dicing process for producing MEMS components

A method includes: in a semiconductor wafer having a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a front surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer, wherein forming the porous region comprises bringing in contact a porosifying agent with the front surface of the first semiconductor layer and applying a voltage between the first semiconductor layer and a first electrode that is in contact with the porosifying agent, wherein applying the voltage comprises applying the voltage between the first electrode and an edge region of the first semiconductor layer.

Method of porosifying part of a semiconductor wafer

A method of forming a semiconductor device, including forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate, increasing the porosity of the first semiconductor layer, first annealing the first semiconductor layer at a temperature of at least 1050&#xb0; C., forming a second semiconductor layer on the first semiconductor layer and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer.

Methods for forming a semiconductor device

Provided is a parent substrate that includes a central region and an edge region. The edge region surrounds the central region. A detachment layer is formed in the central region. The detachment layer extends parallel to a main surface of the parent substrate. The detachment layer includes modified substrate material. A groove is formed in the edge region. The groove laterally encloses the central region. The groove runs vertically and/or tilted to the detachment layer.

Parent substrate, wafer composite and methods of manufacturing crystalline substrates and semiconductor devices

A method includes: in a semiconductor wafer including a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a first surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer.

Method for partially removing a semiconductor wafer

One or more semiconductor manufacturing methods and/or semiconductor arrangements are provided. In an embodiment, a silicon carbide (SiC) layer is provided. The SiC layer has a first portion overlying a second portion. The first portion has a first side distal the second portion and a second side proximal the second portion. The first portion is converted into a porous layer overlying the second portion. The porous layer has a first side distal the second portion and a second side proximal the second portion. The porous layer is removed to expose a first side of the second portion. After removing the porous layer, the first side of the second portion has a surface roughness less than a surface roughness of the first side of the first portion and/or less than a surface roughness of the first side of the porous layer.

Semiconductor surface smoothing and semiconductor arrangement

A substrate wafer arrangement includes a substrate layer having a first main side and a second main side opposite the first main side, the first main side being a front-side and the second main side being a back-side, the substrate layer further having a plurality of semiconductor chips. A polymer structure arranged between the plurality of semiconductor chips extends at least from the front-side of the substrate layer to the back-side of the substrate layer and protrudes from a back-side surface of the substrate layer. The polymer structure separates a plurality of insular islands of conductive material, each insular island corresponding to a respective semiconductor chip of the plurality of semiconductor chips. Semiconductor devices produced from the substrate wafer arrangement are also described.

Semiconductor chip including back-side conductive layer

According to an embodiment of a method described herein, a silicon carbide substrate is provided that includes a plurality of device regions. A front side metallization may be provided at a front side of the silicon carbide substrate. The method may further comprise providing an auxiliary structure at a backside of the silicon carbide substrate. The auxiliary structure includes a plurality of laterally separated metal portions. Each metal portion is in contact with one device region of the plurality of device regions.

Semiconductor device and method of manufacturing a semiconductor device

According to various embodiments, a support table may include: a baseplate including a support structure, the support structure defining a support region over the baseplate to support at least one of a workpiece or a workpiece carrier therein; and one or more light-emitting components disposed between the baseplate and the support region. The one or more light-emitting components are configured to emit light into the support region.

Support table, support table assembly, processing arrangement, and methods thereof

A method of manufacturing a semiconductor device includes: forming one or more device epitaxial layers over a main surface of a doped Si base substrate; forming a diffusion barrier structure including alternating layers of Si and oxygen-doped Si in an upper part of the doped Si base substrate adjacent the main surface of the doped Si base substrate, in a lower part of the one or more device epitaxial layers adjacent the main surface of the doped Si base substrate, or in one or more additional epitaxial layers disposed between the main surface of the doped Si base substrate and the one or more device epitaxial layers; and forming a gate above the diffusion barrier structure.

Method of forming oxygen inserted Si-layers in power semiconductor devices

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Villach, Austria

Bernhard Goller