Samsung Electronics Co., Ltd.

Seoul National University

Snu Rdb Foundation

Postech Academy-industry Foundation

Bernhard Egger

Dong-Hoon Yoo

Won-Sub Kim

Tai-song Jin

Jin-Seok Lee

Il-hyun Park

Hee-Jin Ahn

Soo-Jung Ryu

Yeon-Gon Cho

Soo-jung Ryu

Dong-hoon Yoo

Min-Wook Ahn

Younghyun Cho

Su-Rim Oh

Jaejin Lee

Woong Seo

Young-chul Cho

Sun-hwa Kim

Tae-Wook Oh

Choon-Ki Jang

Won-sub Kim

Jae-Jin Lee

Suk-jin Kim

Seong-Hoon Jeong

Donghoon Yoo

Seong-Hun Jeong

Yoon-Jin Kim

Sung-Joo Yoo

Min-Ju Lee

Yeon-bok Lee

Hong-Gyu Kim

Taisong Jin

Hyemi Min

Ho-chan Lee

Young-Lak Kim

Hong-June Kim

Daeyong Shin

Changyeon Jo

An apparatus includes a processor configured to generate each of intermediate representation codes corresponding to each of a plurality of loop structures obtained that corresponds to a neural network computation based on an input specification file of hardware; schedule instructions included in each of the intermediate representation codes corresponding to the plurality of loop structures; select, based on latency values predicted according to scheduling results of the intermediate representation codes, any one code among the intermediate representation codes; and allocate, based on a scheduling result of the selected intermediate representation code, instructions included in the selected intermediate representation code to resources of the hardware included in the apparatus.

Apparatus and method with neural network computation scheduling

Provided are computing devices, each including a plurality of cores, and methods of allocating power to the plurality of cores. The computing device includes: a control core group including a plurality of control cores, the control core group configured to allocate a power budget to processing cores according to an energy management policy and state information of the processing cores, and transmit the allocated power budget to at least one of a lower control core and the processing cores; and a processing core group including at least one or more of the processing cores, the processing core group configured to perform computations based on the power budget allocated by the control core group, and transmit state information of the processing cores to the control core group, the state information of the processing cores having been modified based on the computations performed.

Computing devices and methods of allocating power to plurality of cores in each computing device

A method of controlling a multi-core processor includes allocating at least one core of the multi-core processor to at least one process for execution; generating a translation table with respect to the at least one process to translate a logical ID of the at least one core allocated to the at least one process to a physical ID; and controlling the at least one process based on the translation table generated with respect to the at least one process.

Multi-core processor and method of controlling the same using revisable translation tables

A multi-core computing device includes a control core group having first low-level control cores and a processing core group. The control core group allocates work groups for executing an Open Computing Language (OpenCL) kernel to the first low-level control cores and first processing cores among the processing core group. The processing core group performs processing of the work groups allocated by the control core group outputs results of the processing. The control cores are hierarchically grouped.

Method of processing OpenCL kernel and computing device therefor

Methods and apparatuses are provided for compressing configuration data. The configuration data, which includes control data corresponding to at least one processing unit used in each of a plurality of cycles, is stored. A plurality of processing units of a reconfigurable processor is divided into a plurality of groups. The configuration data is partitioned into a plurality of pieces of sub-configuration data. Each piece of sub-configuration data corresponding to a respective one of the plurality of groups. If a plurality of adjacent cycles include identical control data, the configuration data is compressed by deleting control data of all but one of the plurality of adjacent cycles, for each sub-configuration data.

Electronic device, reconfigurable processor and controlling methods thereof

A dynamic library profiling method and a dynamic library profiling system including writing a first break point instruction at a start address of a dynamic library function, recording a first event count value that is a process performance management unit (PMU) count when a target process executes the first break point instruction, writing a second break point instruction to a return address of the dynamic library function, and calculating a PMU count generated in a processor core while the dynamic library function is executed, by comparing the recorded first event count value with a second event count value that is a process PMU count when the target process executes the second break point instruction, wherein the process PMU count is a cumulative value of PMU counts generated in the processor core while the target process is executed.

Dynamic library profiling method and dynamic library profiling system

Provided is a reconfigurable processor capable of reducing the routing processing time of routing nodes by driving the routing nodes at a greater frequency than a driving frequency of the processing elements. The reconfigurable processor includes one or more processing elements configured to be driven at a first driving frequency, and one or more routing nodes configured to be provided on paths that are formed between the processing elements, and to be driven at a second driving frequency that is greater than the first driving frequency.

Reconfigurable processor with routing node frequency based on the number of routing nodes

An apparatus for processing an invalid operation in a prologue and/or an epilogue of a loop includes a register file including a first region for storing a data validity value indicating whether data is valid or invalid, and a second region for storing the data; and a functional unit configured to determine whether an operation is valid or invalid based on a value of a first region of each of one or more input sources received from the register file, and output a destination including a value based on the value of the first region of each of the input sources.

Apparatus and method for processing invalid operation in prologue or epilogue of loop

An apparatus and method for generating a very long instruction word (VLIW) command that supports predicated execution, and a VLIW processor and method for processing a VLIW are provided herein. The VLIW command includes an instruction bundle formed of a plurality of instructions to be executed in parallel and a single value indicating predicated execution, and is generated using the apparatus and method for generating a VLIW command. The VLIW processor decodes the instruction bundle and executes the instructions, which are included in the decoded instruction bundle, in parallel, according to the value indicating predicated execution.

Apparatus and method for generating VLIW, and processor and method for processing VLIW

Provided is a reconfigurable processor that may process a first type of operation in first mode using a first group of functional units, and process a second type of operation in second mode using a second group of functional units. The reconfigurable processor may selectively supply power to either the first group or the second group, in response to a mode-switch signal or a mode-switch instruction.

Reconfigurable processor using power gating, compiler and compiling method thereof

An instruction compressing apparatus and method for a parallel processing computer such as a very long instruction word (VLIW) computer, are provided. The instruction compressing apparatus includes a bundle code generating unit, an instruction compressing unit, and an instruction converting unit. The bundle code generating unit may generate a bundle code in response to an input of instructions to be compressed. The bundle code may indicate whether a current instruction group is terminated, and also whether an instruction group following the current instruction group is a no-operation (NOP) instruction group. The instruction compressing unit may remove a NOP instruction and/or a NOP instruction group from the input instructions according to the generated bundle code. The instruction converting unit may include the generated bundle code in the remaining instructions which have not been removed by the instruction compressing unit.

NOP instruction compressing apparatus and method in a VLIW machine

A register file is provided. The register file includes a plurality of registers configured to form at least one register cluster, each of the registers being configured to have a virtual index defined for each cluster and a physical index defined for each register, and an index converting unit configured to convert the virtual index to the physical index.

Register file and computing device using the same

A reconfigurable array is provided. The reconfigurable array includes a Very Long Instruction Word (VLIW) mode and a Coarse-Grained Array (CGA) mode. When the VLIW mode is converted to the CGA mode, instead of sharing a central register file between the VLIW mode and the CGA mode, live data to be used in the CGA mode is copied from the central register file to local register files.

Analyzing data flow graph to detect data for copying from central register file to local register file used in different execution modes in reconfigurable processing array

A method for verifying an operation of a reconfigurable processor is provided. The method includes generating a random test program using a test description and an architecture description, executing the generated random test program in the reconfigurable processor and in a simulator, and then comparing types of output values in the execution result.

Method for verification of reconfigurable processor

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Seoul, South Korea

Bernhard Egger